搜索资源列表
spi
- SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
FPGASPI
- 用FPGA实现主SPI程序,包含开发工程、测试文件和源文件代码-fpga design the SPI code
spi_master_control
- VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
spi_master
- SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer
l1ghVhVI
- The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
modelsim
- verilog SPI master 的完整实验报告 仅供参考 切勿抄袭-verilog SPI master
verilog-SPI-Controler
- 使用Verilog语言实现的SPI控制器，包括SPI主机和从机代码。-Using the Verilog language implementation of SPI controllers, including SPI master and slave codes.
spi
- spi时序控制程序。在fpga中，数据传输等都会由spi进行与主控的交换，此程序用于在数据传输中spi部分的时序控制等。-The spi Timing control procedures. In fpga, data transmission, and will by spi master exchange spi part of this procedure is used in the data transmission timing control.
SPI
- spi master code for fpga quartus altera
SPI-verilog
- spi master code for fpga quartus altera
SPI-Master-Core-DAC-ADC-spartan
- SPI Master Core for spartan (ADC, DAC) vhdl code
SPI-Master
- 有关Verilog的SPI通信的代码,可以应用于FPGA的通信-this is verilog code about SPI
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
spi-master
- code for Master side
SPI-Master-master
- Use code for Maser SPI
SPI_master
- spi-master模块的verilog(simple program for SPI-Master)
Nitro-Parts-lib-SPI-master
- Nitro-Parts-lib-SPI Verilog SPI master and slave
spi_sign_tap2
- 实现了SPI主设备的功能 CPOL=1 CPHA=1,同时包含了PRBS9的数据生成模块，也可以切换为发送固定的数(SPI MASTER CPOL=1 CPHA=1)
spi master slave
- SPI master slave (fpga/verilog)