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spi
- VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits
spi slave
- SPI 接口的VHDL和Verilog实现。slave模式
slave_spi_ctrl.rar
- SPI 的FPGA控制源代码，用于一般通用的SPI技术，FPGA/CPLD控制的AD数据采集,SPI control course code
SimpleSpi
- SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.
SPI_Slave
- SPI Slave example (VERILOG HDL)
SPI_slave-fpga_arm
- 使用SPI接口，使得FPGA与ARM进行通讯. 设置寄存器和读取数据-communicateion FPGA and ARM using SPI
CC2500programmingusingAlteraFPGA
- This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
l1ghVhVI
- The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
spi
- this the SPI slave module -this is the SPI slave module
FPGA-SPI-Slave
- SPI通信基于NI FPGA，利用FPGA硬件对SPI通信进行解析。-SPI communication based on NI FPGA。Build the communication between PC and SPI device
spi
- Altera Cyclone SPI-slave vhdl module
spislave_latest.tar
- SPI接口的verilog代码，本代码是从机代码。-SPI interface verilog code, the code is slave machine code.
spi
- spi slave verilog代码 spi slave verilog代码 spi slave verilog代码-spi slave verilog code spi slave verilog code spi slave verilog code
SPI-Verilog-123
- spi slave code s pi slave code spi slave code -spi slave code spi slave code spi slave code spi slave code
spi
- spi的从机模式，实现数据双向传输，本人用于aes机密模块的数据传输-spi slave mode
Nitro-Parts-lib-SPI-master
- Nitro-Parts-lib-SPI Verilog SPI master and slave
spi_slave_test
- 实现spi协议的从机代码，亲测可用。按照字节接收，发送可以实现一次发送19字节，可按照需要更改。(The implementation of the code of the SPI slave protocol is available. By byte received, sending can be sent to send 19 bytes at a time, which can be changed as needed.)
spi_8r8w
- 同时实现多个SPI从设备的连续读写，读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)
spi_slave
- 使用VHDL语言写的程序，利用SPI协议实现串并转换电路(Programs written in VHDL language and series-to-parallel conversion circuit implemented by SPI protocol)