搜索资源列表
SRAM@DMA实验
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
altera_sdram
- Simple SDRAM controller source code for Altera DE2 board
fpga_sram
- Altera cyclone ep1c6对sram idt71系列的读写时序控制-Altera cyclone ep1c6 of sram idt71 series of read and write timing control
UART_DMA
- 基于ALTERA公司的NIOSII的串口通信DMA传输设计-NIOSII based on ALTERA s DMA transfer of the serial communication design
de2_lcm_ccd_sram
- 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
SRAM_Controller
- Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
das3580sch
- das3580开发板原理图，■ Altera CycloneII EP2C8Q208C8N 的FPGA器件； ■ EPCS4 – 4Mbit 串行配置器件； ■ JTAG和AS双模式下载口； ■ 512Kbyte 10ns级SRAM器件构成双数据通道； ■ Cy7c68013a_128axc高性能USB2.0控制芯片；-das3580 development board schematics, ■ Altera CycloneII EP2C8Q208C8N the FPG
qdr2_sram
- qdr2 sram 在altera 平台上的实际使用-qdr2 sram platform in the actual use of altera
SRAM_1wait
- The aim of this vhdl file is to create a simple interface betwhen the sram and a basic processor on a semisync data bus. This was made using the test board DE2 from Altera.
ALTERA_SRAM_IP
- ALTERA公司的SRAM IP核，加快设计流程-ALTERA company SRAM IP cores, speeding up the design process
vga_memory
- 基于ALTERA DE2 开发板开发的关于SDRAM，SRAM以及FlashMemory的程序-ALTERA DE2 development board based on the development of SDRAM, SRAM and procedures FlashMemory
DE2_USB_API
- 基于altera DE2开发板的USB应用程序，可以实现对FPGA的各项控制，包括输入数据到SRAM中，更换VGA显示器显示的图片等-Based on altera DE2 development board USB application process can be achieved with the control of the FPGA, including the input data to the SRAM, the replacement of VGA display pictur
sram_test
- SRAM Verilog 测试代码。可控制Sram读写。代码来自ALTERA红色飓风开发板资料。-SRAM Verilog
05_NIOS_SRAM
- 利用FPGA的NIOS 2控制SRAM。FPGA的型号为Altera 的Cyclone 4。-Of FPGA NIOS 2 control SRAM. Altera' s FPGA model for the Cyclone 4.