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uart_vhdl
- 是使用VHDL语言编写的基于FPGA的uart的源代码！-VHDL language is to use FPGA-based uart source code!
uart
- 用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program
LC_txmit
- FPGA UART transmit and so on
uart_0910
- uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of fr
T_uart
- CPLD发送模块的实现代码,设计按键检测模块，并将键值通过构造的UART发送模块发送到串口调试工具中查看。--发送格式：1位起始位+8位数据位+1位停止位=10位-CPLD implementation of the code to send the module to design key detection module, and key by constructing the UART to send the module to send to the serial port debugg
lab4
- vhdl uart lab ENTITY uart IS PORT ( SIGNAL clock,reset : IN STD_LOGIC SIGNAL sdatain : IN STD_LOGIC SIGNAL oready, sdataout : INOUT STD_LOGIC SIGNAL iready : INOUT STD_LOGIC SIGNAL charin : INOUT STD_L
example7
- 基于NIOSI II 的UART的使用 希望对大家有用啊！！！欢迎下载啊-It s a NIOS II code for UART
prob1
- UART program for fun-UART
UART
- 基于NIOS2的串口初始化设计程序，在应用中只要加上这个初始化就可完成所有的初始化任务-Based on the serial port initialization NIOS2 design process, in applications, coupled with this initialization can be completed as long as all of the initialization task
uart
- VHDL编写的异步输入输出接口控制程序 从网易博客上下的-VHDL write asynchronous input and output interfaces control the process from top to bottom Netease blog
VHDLtransmitter
- 这是我做UART时候做的一个发送器的源码，希望对大家有用。-This is what I did do a UART transmitter when the source and hope for all of us.
UARTE
- 用VHDL语言编写的串口通讯模块，可以实现发送和接受功能。-A UART module writen in VHDL.
SOPC_UART
- altera公司的ep1c240c8n，串口调试程序vhdl\nios ii8.0代码等-altera company ep1c240c8n, serial debugger vhdl \ nios ii8.0 code. .
uart
- 程序说明: 本次实验控制开发板上面的串口，与PC机进行通信，并在串口精灵里面显示字符。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: The experimental control development board above the serial port to communicate wit
edaok_UART_FPGA
- 用FPGA实现UART的串口通信，可以设置数据位，校验位，奇偶校验等-With the FPGA to achieve UART serial communication, you can set the data bits, parity bit, parity, etc.
WAVE6000
- 基于VHDL语言设计一个全双工UART电路，主要模块：波特率模块、数据发送模块、数据接收模块。-VHDL language design based on a full-duplex UART circuit, the main modules: module baud rate, data transmission module, the data receiver module.
test_state
- VHDL code for UART transmission & reception.
uart_tx
- Interface for Transmitter UART
Verilog_uart
- UART communication code
uart_tx
- UART EDGE TRIGGERED ONE SHOT VHDL