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micro uart
- 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
UART
- 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
uart
- uart using verilog hdl
uart_txd
- 基于verilog hdl的UART串口发送子程序。-Verilog hdl a UART-based serial port to send subroutine.
i2c_AT24C04_Verilog
- 用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
uart
- 基于verilog HDL编写的串口通讯接口uart程序-Prepared based on verilog HDL uart serial communication interface program
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
UART
- verilog hdl UART de bo xing-verilog
RS232
- It s combination logic for UART. Edited in verilog-HDL.
uart
- uart设计 包括调试程序 uart设计 包括调试程序-uart verilog HDL uart verilog HDL uart verilog HDL uart verilog HDL uart verilog HDL uart verilog HDL
UART
- Verilog HDL写的实现ＵＡＲＴ收发程序-Realization of Verilog HDL UART receive written procedures
UART
- this a uart verilog HDL design code-this is a uart verilog HDL design code
uart
- uart发射机Verilog HDL代码-Verilog HDL code uart transmitter
uart
- FPGA UART通讯模块，基于verilog HDL语言-FPGA UART communication module, based on the verilog HDL language
uart
- verilog hdl 编写的串口接收发送-send rec data with verilog hdl
mini-UART
- URAT资料，用verilog HDL编写，具有完整的信号描述和功能-URAT data write complete signal descr iption and function, with verilog HDL
Verilog-HDL
- Verilog HDL设计+Modelsim仿真UART-Verilog HDL Designing+ Modelsim UART simulation
uart-of-fpga
- FPGA实现UART通信程序，verilog hdl语言实现的，好用-UART of FPGA
uart
- 电脑端发送数据与FPGA接收数据程序，uart模块，以及一部分项目里包含的其他的程序(Program for sending data from computer and receiving data by FPGA, UART module)