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RS232串口通信协议
- RS232串口通信协议，verilog实现，通过FPGA完全调通。,RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
RS232_control
- verilog RS232信号解码模块。为在FPGA中的verilog代码。-verilog RS232 control module。
rs232
- 用verilog实现的RS232时序控制，完整可以使用的-RS232 verilog implementation with timing control, you can use the full
URAT
- Verilog硬件描述语言，RS232串口发送接收程序-Verilog hardware descr iption language, RS232 serial port send and receive program
RS232_pro
- RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
RS232_project
- 串口通讯 rs232 verilog程序，一次接受传送8bits-rs232 verilog project，reciver or trancimiter 8 bits onece
RS232
- RS232_串口通信的发送端verilog源程序代码-RS232_ serial communication sender verilog source code
uart
- RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
rs232-Quartus
- 利用verilog語法,來達成串口rs232的功能-Using verilog syntax, to achieve the functions of serial rs232
RS232
- 实现FPGA的RS232串行通信，采用verilog语言编写，下载到芯片上就可以使用-FPGA implementation of the RS232 serial communication, using verilog language, can be downloaded to the chip using
rs232
- 本设计是PC和FPGA的串口通信的程序，用的是VERILOG语言，调试成功，用户可根据自己的项目稍作改动。-The design is a PC and the FPGA' s serial communication procedures, using a VERILOG language, debugged, the user can make a little change according to their own projects.
rs232
- 基于VERILog的RS232模块的程序，收发两个模块都有-The RS232 module based VERILog program, send and receive two modules have
RS232
- It s combination logic for UART. edited in verilog-HDL
RS232
- It s combination logic for UART. Edited in verilog-HDL.
rs232
- verilog语言编写，RS232通讯程序设计-verilog language, RS232 Communication Program Design
my_uart1_VERILOG_using-PLL
- Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using P
verilog串口收发模块程序
- 基于verilogHDL语言的RS232串口收发模块程序
Verilog-RS232
- 本程序是在FPGA里面模拟RS232串口，并在已调试成功。-This procedure is simulated in FPGA RS232 serial port, and in the debugging success
RS232
- 基于quartusii的用verilog编写的rs232串口程序(QuartusII based on Verilog prepared by the RS232 serial procedures)