搜索资源列表
FIFO
- 基于vhdl语言的fifo设计，方便你了解先进先出理论-Based on the the vhdl language of fifo design, allowing you to understand the first-in, first-out theory
fifo
- 先进先出存储器的接口设计，采用VHDL语言-FIFO memory interface design, using VHDL language
FIFO
- FIFO在VHDL上的实现。没有注释，较为完善，已通过编译。-FIFO implementations in VHDL. No comment, more perfect, has compiled.
FIFO
- FIFO的资料，包括文档说明已经一个VHDL文件。-FIFO data, including document describes a VHDL file.
FPGA-FIFO-VHDL
- 这是一个基于FPGA的异步FIFO设计，利用的VHDL硬件描述语言，内容分析清楚，附带完整代码-This is an FPGA-based asynchronous FIFO design, the use of VHDL hardware descr iption language, content analysis, with complete code
Async-FIFO-VHDL
- 异步FIFO VHDL代码实现，包括：async_fifo_show_ahead.vhd， async_fifo_show_ahead_rd_task_logic.vhd，async_fifo_show_ahead_wr_task_logic.vhd， sync_r2w.vhd，sync_ram_std_dc.vhd，sync_w2r.vhd-The asynchronous FIFO VHDL code implementation, including: async_fi
vhdl-Language-routine-highlights
- 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
VHDL-memory
- 存储器的VHDL描述，包括ROM,RAM,FIFO,stack等多种类型-design of memory by VHDL
SLAVE-FIFO-8BITS
- EZUSB FX2 的 SLAVE FIFO例程，包含8051的Firmware以及FPGA的FIFO控制代码 -EZUSB FX2 SLAVE FIFO sample program, including the 8051 firmware, and 8-bit VHDL slave FIFO interface code for FPGA
fifo
- FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
Asynchronous-FIFO
- Asynchronous FIFO Implementation in VHDL
fifo
- 设计一个同步的双端口fifo ,大小为8*128。-Designing a synchronous dual-port 8* 128 fifo using VHDL.
FIFO
- 用VHDL语言实现一种异步FIFO，并做时序仿真和功能仿真检验正确性。-Achieve an asynchronous FIFO using VHDL language, and do functional simulation and timing simulation test accuracy.
FIFO
- 用VHDL语言写的FIFO IDT7205驱动程序。时序仿真无误！-VHDL language used to write the FIFO IDT7205 driver. Timing simulation is correct!
proje2
- it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
fifo
- VHDL code for DATA PATH for performing A=A+3 and A=B+C TO DESIGN AND SIMULATE DATA PATH FOR PERFORMING A=A+3 AND A=B+C USING ONLY ONE ADDER.
VHDL-8bitFIFO
- FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它只的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等，本程序实现8位的FIFO功能,三位格雷码可表示8位的深度。-THE WIDTH of THE FIFO: namely information in English often see THE WIDTH, it is only a FIFO data read and write operations, as has 8 bit or 16 bit M
FIFO
- vhdl code for FIFO implementation
CCD_Array
- Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
fifo_FPGA
- 68013 FIFO 接口程序，USB开发、VHDL开发(68013 FIFO USB VHDL FPGA)