搜索资源列表
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
The_design_of_MIPS_CPU(VHDL)
- MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
mips1
- Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
mipsfinal
- 用vhdl设计的一个mips小型cpu，不带流水，有r类，i类，j类指令都有~·-Using vhdl design a mips small cpu, with no running water, there are r class, i type, j class instruction have ~*
MIPS_CPU
- MIPS结构的CPU，采用VHDL编码，附带验证程序，能够跑题hash算法，流水灯，求π程序-MIPS structure of the CPU, using VHDL coding, with the verification process, to get off track and hash algorithms, water lights, find π procedures
mips
- MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
mips_cpu_final
- 一个8位的mips cpu，采用VHDL语言编程。-this is a 8 bits mips cpu core which is writed by vhdl
project3
- mips single cycle cpu
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
VHDL-for-Datapath
- MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg
MIPS_Pipelined_CPU
- MIPS Pipelined CPU written on VHDL with commands, 5 stage pipeline
vhdl-pipeline-mips0
- MIPS CPU WITH PIPELINE procesador MIPS-FZA -- Autor: mahdi ahmadi -- Email: mahdi@fza.ir -- mahdifza@yahoo.com -- -- Version: 1.0
cpu
- 用vhdl实现了具有流水的cpu，实现30条基于mips指令的指令集-Achieved with vhdl cpu with water, to achieve 30 mips instruction based instruction set
OpenMIPS_VHDL_study_v1.0
- 10天实现OPENMIPS处理器-VHDL版[内有详细代码，testbench和设计文档，十天教你学会MIPS架构CPU设计]-10 days to achieve the OPENMIPS processor-VHDL version [within a detailed code, testbench and design documents, ten days to teach you to learn MIPS architecture CPU design]