搜索资源列表
viterbi
- 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明
viterbi
- (2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过
viterbi
- 卷积码编码及其Viterbi译码的实现
(2,1,3)卷积码编解码
- (2,1,3)卷积码编解码，viterbi译码
Viterbi_IP.rar
- viterbi译码器的IP核，可以直接编译使用,viterbi decoder IP core, the compiler can directly use
viterbi.rar
- 这是一个用VERILOG HDL语言编写的viterbi译码程序,This is a language VERILOG HDL by the viterbi decoding process
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Viterbi
- 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
Viterbi
- Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
VB_decode
- Viterbi译码的VHDL代码，并且附有详细说明-Viterbi decoding of the VHDL code, and accompanied by a detailed descr iption
Viterbi_decoder
- Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog
viterbidecoder
- viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
viterbi
- 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Viterbi_verilog
- 在ISE环境下用Verilog语言编写的卷积码程序及Viterbi译码程序-Under the ISE Verilog language with procedures and Viterbi convolutional code decoding program
viterbi
- 高效率的viterbi译码，对通信中的卷积码进行译码-Efficient viterbi decoding of communications for decoding convolutional codes
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
Viterbi_Verilog
- viterbi译码的verilog实现,提供相应的原程序代码和testbench -viterbi decoder verilog implementation
Viterbi-Compiler-User-Guide-(ver
- Altera的Viterbi译码IP软核使用说明-User guide of Viterbi decoder IP core.
viterbi-ip-core-using-mothed
- FPGA的Viterbi译码器IP 核的使用说明，简单方便，一目了然。还能进行tcm译码，功能强大呀-Instructions for use of the FPGA Viterbi decoder IP core, easy glance. Can tcm decoding powerful!
（2,1,3）卷积编码和viterbi译码
- 自己写的（2,1,3）卷积编码器和viterbi译码，测试已通过