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一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
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超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
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32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
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用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
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浮点数加/减法器的设计
规格化的浮点数运算器
IEEE标准754 单精度-Floating-point add/subtract device design normalized floating-point arithmetic unit single-precision IEEE Standard 754
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浮点加法器的用Verilog实现，32位的浮点加法器-Floating point adder Verilog
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Floating-point arithmetic (2008), ADD, SUB, MUL, SQRT, FUNCTION (IEEE 754-1985 Standard, IEEE 854-1987 Standard, New IEEE 754-2008 Standard)-Floating-point arithmetic (2008), ADD, SUB, MUL, SQRT, FUNCTION (IEEE 754-1985 Standard, IEEE 854-1987 Stand
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32位单精度浮点运算单元,遵从IEEE 754标准，持浮点加、减、乘、除等运算。-32-bit single-precision floating-point unit；comply with the IEEE 754 standard；support floating-point add, subtract, multiply operations.
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floating point add unit
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floating point fused add-subtract unit
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