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ADC_VHDL2
- analog to digital converson programmed in VHDL
adc
- vhdl实现对模数转换芯片adc0832的控制,程序采用的是状态编码输出.-VHDL realization of analog-digital conversion chip adc0832 control, procedures using state of the output encoding.
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of
ask100
- 时钟同步模块：通过时钟同步模块，将模拟前端提取的时钟信号和数据进行同步，使得数字后端可以正确读取数据。-Clock synchronization module: The clock synchronization module, the analog front-end of the clock signal extraction and data synchronization, making the number of back-end data can be read correctly
RAM
- 用VHDL编写一个字长16位，容量128B的RAM控制实现程序，并进行设计综合和功能模拟 。含源程序，及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental
pcm
- 在光纤通信系统中，光纤中传输的是二进制光脉冲"0"码和"1"码，它由二进制数字信号对光源进行通断调制而产生。而数字信号是对连续变化的模拟信号进行抽样、量化和编码产生的，称为PCM（pulse code modulation），即脉冲编码调制。这种电的数字信号称为数字基带信号，由PCM电端机产生。-In optical fiber communication systems, fiber-optic transmission of light pulses is a binary "
dac
- Digital to Analog Converter code VHDL
oscillograph
- 用VHDL编写的oscillograph数字部分源代码，在Altera FPGA上跑通。直接把模拟部分输入输出AD，DA信号接入本模块即可。-Digital oscillograph with the written part of the VHDL source code, in the Altera FPGA on the run-pass. Directly to the analog input and output AD, DA signal can access this modul
memtest
- 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)
coding_and_synthesis_with_verilog
- In the semiconductor and electronic design industry, Verilog is a hardware descr iption language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verificati
EDA
- VHDL完成计价器，模拟出租车正常加速，暂停，停止等状态，在加速，暂停，开始，停止均有提示灯表示，起步7.5元，超过3公里2.2/km,超过20元，每公里3.3-VHDL complete meter, analog taxi normal speed, pause, stop and other states, in acceleration, pause, start, stop lights that are prompt, start $ 7.50 more than 3 km 2.2/
dff1
- 本程序使用vhdl语言编写，能够使用ALTERA CPLD-EPM3128A 模拟出一个D触发器。-This program written in vhdl language, be able to use of ALTERA the CPLD analog-EPM3128A, a D flip-flop.
ADC
- analog to digital converson programmed in VHDL
vga
- vga This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a