搜索资源列表
AMBA-Specification-Rev-2.0
- AMBA2.0总线协议详细介绍，共230叶英文资料-AMBA2.0 bus protocol details, a total of 230 leaves information in English
eetop[1].cn_axibusregslice
- axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
Micrium_Microblaze_uCOS-II-AXI
- 支持xilinx ise designer 14.x的microblaze AXI总线 ucosii操作系统。-Support xilinx ise designer 14.x for microblaze AXI bus ucosii operating system
ddr_top
- verilog语言ddr3读写程序，axi总线协议，用于ddr3读写测试-ddr3 read and write
axi_jesd204b
- ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
axi_lite_user
- axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)
AXI slave
- 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
CV_FPGA_to_HPS_Bridge_Design_Example
- FPGA通过AXI总线传输数据给ARM,ARM使用DMA方式接收数据！(FPGA to ARM Bridge design example)
slave
- xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
axi_ad9361
- AXI_AD9361 的 verilog 驱动工程，包含数据接收，数据发送 AXI总线 ，全部是verliog实现(AXI_AD9361's Verilog drive project, including data reception, data transmission AXI bus, all verliog implementation)
cpu_uart_leds_ip
- 基于Altera 的一个IP核，能完成串口收发,以及自定义IP,可以作为自定义AXI总线接口的例子(Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example)
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
src
- 基于AXI 总线的可配置脉冲计数器，可以配置计算脉冲的个数。(The configurable pulse counter based on AXI bus can be configured to calculate the number of pulses)