串并滤波器(FPGA源码),基于QuartusII开发设计实现的串并滤波器.-String and filter (FPGA source code), based on the achievement of development and design of QuartusII and filter string.

数字化中频接收机，用在AD之后的带通滤波器，VERILOG描述，32阶-Digital IF receiver, used in the AD after the bandpass filter, VERILOG descr iption, 32-step