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PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
cache
- 缓存器 cache verilog 欢迎下载偶-cache verilog
slice
- A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually inter
fifo
- 用vhdl语言实现对八位数据进行缓存的控制-With VHDL language implementation to eight of the data cache of control
RCQ208_V3_24TFT
- Quartus NIOS例程，控制320*240TFT液晶显示，包括汉字、字符显示及显示缓存SDRAM控制驱动-Quartus NIOS routines, control 320* 240TFT LCD, including Chinese characters, character display and display control drive cache SDRAM
ov5640
- fpga控制CMOS相机ov5640采集图像，包括相机配置，ddr缓存，vga显示三个模块。直接可用-fpga control CMOS camera ov5640 capture images, including camera configuration, ddr cache, vga three display modules. Directly available