It is a complete project of Cache Interface Controller programmed in VHDL using the logic of Moore State Machine

本工程实现两路视频信号阿尔法通道混合(alpha blend), 视频信号黑点中心 点扫描定位，期间用到视频帧缓存（frame cache）、视频信号缩放(scaler)等，且用到ram、DDR2等作为缓存，是很值得参考的视频图像处理工程。-scaler,alpha blend,ddr2 controller,center scan, frame cache, dpram, etc by verilog, include code and discr iption

This project is to develop a direct mapped cache controller for embedded applications. Key Design Features - Direct mapped with configurable address size, line size and number of cache lines - Non Pipelined architecture - No Cache f