搜索资源列表
cal_verilog
- 计算器芯片的verilog实现代码！ 时序仿真成功-calculator chips to achieve the Verilog code! Timing simulation success
codeofvhdl2006
- 【经典设计】VHDL源代码下载～～ 其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】 基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】
calculation2
- 用VHDL语言实现0--100范围内简单计算器功能的源代码，包括加减乘除四种运算功能-VHDL 0 -- 100 within a simple calculator function in the source code. including the four arithmetic operations function
vhdlcodeforcalculator
- calculator using VHDL CODE
calculator
- VHDL编写计算器，功能包括：加，减，乘，除。通过keypad输入及输出-Calculator written with VHDL
subadd
- 一个四位二进制加/减运算器。 要求：当控制端G＝0时做加运算，G＝1时做减运算。用发光二极管表示运算结果的正、负。用数码管显示运算结果：加运算时，相加之和不超过15，减运算时，结果可正可负，但都用原码表示。-Plus a four binary/by calculator. Requirements: When the control terminal G = 0 when computing increases, G = 1 when computing reduced. Computin
ALU_VHDL_code
- ALU逻辑运算单元计算器的VHDL源代码，已通过FGPA验证，绝对正确。-ALU ALU calculator VHDL source code has been verified by FGPA absolutely correct.
presentar
- Verilog code calculator, add, rest, multiply, and increment-Verilog code calculator, add, rest, multiply, and increment
calculator
- 此源码为在xilinx环境中用VHDL实现计算器，实例可用xcs40xl-4-pq208戓xc2s100-6pq208FPGA来实现-The source code in xilinx environment using VHDL implementation calculators, examples can be xcs40xl-4-pq208 Ge xc2s100-6pq208FPGA to achieve
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
calc
- 计算器源代码，Quartus II Verilog-Calculator source code, Quartus II Verilog
DDS-program
- DDS芯片中主要包括频率控制寄存器、高速相位累加器和正弦计算器三个部分（如Q2220）。频率控制寄存器可以串行或并行的方式装载并寄存用户输入的频率控制码；而相位累加器根据 dds 频率控制码在每个时钟周期内进行相位累加，得到一个相位值；正弦计算器则对该相位值计算数字化正弦波幅度（芯片一般通过查表得到）。DDS芯片输出的一般是数字化的正弦波，因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-The chips mainly includes DDS frequen
Calculator
- 采用FPGA编写代码，包含了3-8译码器，加法器，减法器，乘法器的功能。-The FPGA write code, including a 3-8 decoder, adder, subtractor, multiplier function.
Calculator_release0506
- 8051計算機原碼，使用c語言編碼，設有16x2LCD-8051 calculator source code
CIII_EP3C40F780C8_37_Calculator
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,简易计算器实验代码-SOPC,CycloneIII，EP3C40F780C8，NIOS II IDE, CALCULATOR code
Calculator
- 4位十进制计算器，有加，减，乘，除四个功能，并有检测代码。-4bit decimal computers, there are add, subtract, multiply, divide four function, and detection code.
calc_16_01_14
- A VHDL code for a simple calculator.It reads the operator and operands form the memory and execute
Calculator
- VHDL计算器，涉及PS2输入，VGA视频输出，加法器，BCD转化。可以通过研究代码学习以上知识-VHDL calculator, involving PS2 input, VGA video output, the adder, BCD transformation. You can learn more knowledge through research code
GCD-CALCULATOR
- GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataPath) the code is synthesize