搜索资源列表
LTC1407A
- LTC1407A仿真 可以模拟其全部功能 具有单端输入 时钟 串行输出-LTC1407A simulation can simulate all the functions in its single-ended input clock serial output
LCD12864
- 利用FPGA编程实现在LCD上显示汉字，非常实用的教程，里面有详细的代码说明，修改后即可实现你的需求。-Using FPGA Programming in LCD display Chinese characters, a very useful tutorial, which has a detailed code instructions can be modified to meet your needs.
imageSample
- 这是一个图象传感器的数据采集程序，用Verilog语言编写，经测试通过，改程序可以作为图像数据采集参考，缩短开发时间。-This is an image sensor data collection procedures, with the Verilog language, has been tested and approved to change the image data acquisition procedure can be used as reference, to shorte
IIC
- 用标准Verilog HDL 语言编写的IIC总线IP核，详细定义了时序及输入输出， 可以直接应用-Standard Verilog HDL language of the IIC bus IP core, a detailed definition of the timing and the input and output, can be applied directly
VGA
- Verilog代码可移植到FPGA上，利用VGA显示图像，适合初学者使用。-Verilog code can be ported to FPGA, using VGA display images, suitable for beginners.
RS232
- 实现FPGA的RS232串行通信，采用verilog语言编写，下载到芯片上就可以使用-FPGA implementation of the RS232 serial communication, using verilog language, can be downloaded to the chip using
subtracter_4
- 好还是verilog，现在你记忆可以，是关于FPGA的设计-Good or verilog, now you can remember, is the design on the FPGA
Verilog_study_book
- 现代计算机与通讯系统电子设备中广泛使用了数字信号处理专用集成电路，它们主要 用于数字信号传输中所必需的滤波、变换、加密、解密、编码、解码、纠检错、压缩、解压缩等操作。这些处理工作从本质上说都是数学运算。从原则上讲，它们完全可以用计算机或微处理器来完成。这就是为什么我们常用C、Pascal 或汇编语言来编写程序，以研究算法的合理性和有效性的道理。-Modern computer and communication systems are widely used in electronic eq
rs232
- 本设计是PC和FPGA的串口通信的程序，用的是VERILOG语言，调试成功，用户可根据自己的项目稍作改动。-The design is a PC and the FPGA' s serial communication procedures, using a VERILOG language, debugged, the user can make a little change according to their own projects.
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
dds
- 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
VerilogFIR
- low pass FIR filter programmed by Verilog, you can change the coefficients in the program to achieve different response
FFT8
- FFT8，8点FFT运算，用verilog vhdl 语言编写，可以应用于64点FFT-FFT8, 8 点 FFT computation, using verilog vhdl language, can be applied to 64-point FFT
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
ps2andverilog
- 仿真已通过验证，并下载到FPGA实验板测试，大家可以下载来学习-Simulation has been validated, and downloaded to the FPGA test board test, you can download to learn ~~~~~
PWM_DA
- 可以产生PWM波形文件 ，熟悉基于FPGA的开发流程 自己写的程序-PWM waveform files can be generated, FPGA-based development process familiar to write their own programs
VGA_char_ROM_success
- Verilog HDL语言编写的基于M4K块配置ROM的字符数据存储VGA显示实验代码，引脚分配适用于21EDA的EP2C8Q208开发板, 详细解说请参见特权同学《深入浅出玩转FPGA》视频教程中的《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》-experimental code written in Verilog HDL language，ROM configuration based on M4K block for the cha
1
- 使用force和release语句，这种方法不能准确反映双向端口的信号变化，但这种方法可以反映块内信号的变化。具体如示：-Use of force and release statements, this method does not accurately reflect the bi-directional port of the signal changes, but this method can reflect the changes in the signal block. Spec
uart
- verilog 语言，uart 测试程序，通过串口能够测试开发板上uart芯片的好坏-uart test module with verilog langunge,it can be used to test the uart ic on your board.
SPItoI2S
- 该文件是I2S 转 SPI的Verilog的源代码，可以在此基础上修改成自己的应用代码-The file is transferred SPI, I2S Verilog source code, you can change the basis of their application code into