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verilog
- 波形发生器，产生4种波形，能够自己手动转换，并能调节输出频率-Waveform generator to produce four kinds of waveforms that can convert your manual, and can adjust the output frequency
waveform_-generator
- 简易信号波形发生器，可以产生四种波形，频率1k-20K步进可调。学习Verilog HDL的好例子。-imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL.
OFDM_retiming
- 基于Verilog的OFDM时钟恢复模块，在做全数字OFDM的时候是关键模块，可以在FPGA上实现。-Verilog-OFDM-based clock recovery module, doing all-digital OFDM time is the key module can be implemented on the FPGA.
USB
- USB控制器的VERILOG工程文件，工程为ISE的，可以编译通过，压箱底的东西了-USB controller VERILOG project file, works for the ISE, you can compile, pressure bottom of things
tft_lcd
- 用verilog写的TFT液晶驱动程序，本程序经下载到开饭板后，能正常运行-Verilog write with TFT LCD driver, this program downloaded to the have dinner plate, can normal operation
DDS
- 能在DDS中用Verilog HDL语言实现FM,AM,FSK,ASK,PSK，结合可编程器件FGPA等等就能实现这些功能 -DDS can be used in Verilog HDL language FM, AM, FSK, ASK, PSK, etc. FGPA programmable devices can be combined to achieve these functions
div_frequency
- 任意分频器，用Verilog HDL实现，只需修改参数可以实现奇数、偶数分频，FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
Verilog----m
- verilog 编写的m 序列，可以直接使用。-verilog written m-sequence can be used directly.
1day11-keyboard
- 清华大学电子课程设计：Verilog语言编写，可在QuartusII完全正确运行，FPGA下载，键盘按键输出相对应数字，有防抖功能-Verilog language, can be run in QuartusII entirely correct, FPGA download, keyboard keys corresponding to the output figures, anti-shake function
verilog
- 都是介绍VHDL的资料，费了好大劲搞到的，很不错，大家可以分享下-CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
DE2-VGA-LED
- verilog HDL 语言编写的，FPGA的数码管和VGA的显示。调用时不必修改源码，只需引脚映射对就可以-verilog HDL language, FPGA digital and VGA display. Call without having to modify source code, you can just pin on the map
Verilog
- 这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。-This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.
can_latest.tar
- 用Verilog写的CAN协议IP核 已经验证可以使用 -CAN protocol written in Verilog IP core has been verified using
Verilog-FIFO
- 可综合的Verilog FIFO存储器，可以实现先如先出的设计-Synthesizable Verilog FIFO memory can be as-first-out design
Matlab-Verilog-Linking
- Matlab Verilog Linking超級完整教學，可以-Matlab Verilog Linking super full of teaching, you can try
FIFO-verilog
- 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design,
verilog-CAN-Controler
- 使用verilog语言实现的CAN控制器代码。-Use the CAN controller verilog language code.
spacewire_src
- opencores上的关于spacewire的初级源码，已经通过板上实验，但是工程应用有待完善，可以作为设计人员的设计参考-opencores on spacewire on the primary source, the board has passed the test, but the engineering applications need to be improved, can be used as design The design reference staff
verilog
- 很好很全的代码，大家可以参考一下，很适合初学者。-a very good code ,all newers for vhdl can refer to it
DDS-VERILOG
- DDS的信号发生器verilog代码 可直接用于编程 已经测试-Verilog code of the DDS signal generator which can be used directly in the programming has been tested