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verilog2
- 用verilog语言编写的按键消抖程序。通过下降沿检测法可以判断出是否按键。压缩包内也包含此按键消抖程序的modelsim仿真文件。-Verilog language with key debounce process. By falling edge detection method can determine whether the key. This compressed package also contains procedures for key debounce modelsim
LCD12864
- 1 fpga驱动lcd液晶12864的verilog源程序 (显示英文,可以在源程序中直接修改成自己想要显示的英文) 2 引脚配置完成,程序已经测试,完全好用 3 使用的FPGA芯片是altera的max2EP2C5T1-1 fpga driver' s verilog source code 12864 lcd LCD (display in English, you can directly modify the source program into what you w
Chapter10
- 第十章的代码。 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
vga_test_313
- VGA显示实验,已测试运行过,学FPGA的朋友可以下下来看看,用verilog写的-VGA display experiments The under test run school FPGA friends can look down to write with verilog
PS2
- 此代码是PS2键盘的Verilog程序,键盘的字符可显示在LCD 1602上,经上板调试程序是可行的-This code is a PS2 keyboard Verilog program, keyboard characters can be displayed on the LCD 1602, after the board debug process is feasible
Phone-meter
- 这是电话计费器的Verilog源程序,已经编译通过,可以直接使用-This is a call accounting device Verilog source code, has been compiled by, can be used directly
tongxin
- 串口与电脑的通信 可以用调试助手 进行试验 采用verilog语言设计 编译已通过-Serial communication with the computer test can be used with debugging assistant compiled verilog language design has passed
chuan2
- 用verilog HDL编写的并串转换模块,在ISE软件仿真过,也可综合-Prepared using verilog HDL and string conversion module, in the ISE software simulation, and can also be integrated
modelsim-win32-6.5-se_Crack
- modelsim-win32-6.5-se 解破文件。 功能全。可以用到2020年。可以用于VHDL,VERILOG, system C 等模拟及混合模拟。-modelsim-win32-6.5-se solutions broken files. full loaded. expired in 2020.. Can be used for VHDL, VERILOG, system C simulation and mixed simulation.
epcs_controller
- 用verilog 语言写的可配置控制器程序用于实现fpga软件程序的存储-Verilog language used to write programs that can configure the controller fpga software programs used to implement the storage
beipin_top
- 次代码利用verilog HDL来描述的,可以实现2倍频功能,只是频率有一点误差。-Times verilog HDL code to describe the use of, 2 octave function can be achieved, but the frequency of a bit error.
fpga-pwm
- 用verilog 语言写的FPGA子程序,环境是quartus II 7.2 已经在EP1C6Q240上测试过,源码包含仿真文件和仿真结果,本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
ad706_7276
- DA7276 的verilog 代码,时序还算精准,可直接复制使用-DA7276 of the verilog code, timing still accurate, can be directly copied using
Walsh
- 利用ISE编写的产生WALSH码的verilog程序,简单易懂,稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码-Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16,32,64-bit code WALSH. .
counter_3
- 三种计数器的verilog实现,二进制计数器,格雷码计数器,约翰逊计数器.初学硬件描述语言可参考。-Three kinds of counter verilog implementation of a binary counter, gray code counter, Johnson counter beginner hardware descr iption language can refer to
bridge
- FPGA和A/D转换芯片ad7862的IP,可实现4路数据的采样和读取。 用verilog实现的-FPGA and the A/D conversion chip ad7862' s IP, can achieve 4-way data sampling and reading. Achieved with verilog
recuart_50m
- 本代码功能为实现接收PC发送的串口数据功能 程序通过quartusII 8.1编译,使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 (开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) 有需要的朋友可以下载参考-The code functions to achieve the receivi
1302write-and-read
- DS1302写读连用程序,可以设置要写的地址,Verilog语言,在板子上跑过的,可以实现功能的-DS1302 write read Ed program can be set to write the address of the Verilog language, in the board runs, can realize the function
led_rotary
- Spartan-3E实验板,基于Verilog实现旋转按钮控制八个LED灯移动方向。- a program by verilog that can control the leds in the spartan-3e lights direction by the rotary button on it.
adc_verilog
- 用verilog编写的ADC控制接口,只需根据具体ADC器件的时序图修改代码就可运行。-ADC prepared with verilog control interface, just depending on the ADC timing diagram of the device can modify the code to run.