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multi-CPU
- Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and
zs
- 基于fpga的数字频率计，verilog编写，可修改闸门宽度0.1s/1s/10s，可测频率1hz~1mhz，包含整个工程，内部分频模块为了仿真方便改小了，后面注释为50mhz晶振下的分频值，可根据需要自行修改-Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire
nexis1
- 用Verilog HDL 状态机实现的驱动数码管显示，是个很不错的模块，可以直接用-Using Verilog HDL state machine driven digital display, is a very good module, can be directly used
TLC5620v
- 本程序是用verilog 状态机编写的tlc5620的驱动程序，可以直接调用-The program is written in verilog tlc5620 state machine driver, you can directly call
11_lcd1602
- 本程序是用verilog 状态机编写的lcd1602的驱动程序，可以直接调用-The program is written in verilog lcd1602 state machine driver, you can directly call
spi_verilog
- 使用verilog编写的spi传输模块，已经通过验证，有仿真文件，可以传输信息。-Prepared using verilog spi transmission module, has been validated with simulation files, you can transfer information.
elevator_v2
- 用verilog语言描述的模拟单电梯的运行过程。方向优先原则。(1)每层电梯入口处设有上下请求按钮（一楼只有上请求，6楼只有下请求），电梯内设有顾客到达层次的停站请求开关。 (2)电梯入口处设有电梯当前所处楼层指示装置及电梯运行模式(上升或下降)指示装置。 (3)电梯每2秒升(降)一层楼。 (4)电梯到达有停站请求的楼层，经过1秒电梯门打开，开门指示灯亮，开门3秒后，电梯进入关门中状态，提示乘客可以按下延迟关门按键，此时指示灯闪烁，2秒后电梯门关闭，电梯继续进行，直至执行完最后一个
chenyu--chengxu
- 用verilog语言编写的串口通信程序,可以作为一个地址选择控制器使用，实现和不同的串口设备通信-Using verilog language serial communication program, can be used as an address selection controller, implementation and communication of different serial devices
cordic
- 用Verilog写的CORDIC算法程序，经验证完全能实现-Using Verilog to write CORDIC algorithm, proven it can achieve the
fenpin
- verilog语言编写的分频程序，可以通过defpram实现任意整数任意占空比分频，有详细注释-divider verilog language program can be achieved through defpram arbitrary integer divide any duty, detailed notes
daba
- 采用verilog 语言编写的打靶程序，配合黑金四代开发板，可以VGA屏幕上显示闪烁打点。打点坐标可以自我设置，也可以由外设用给。-Using verilog language targeting program, with four generations of black gold development board, VGA screen flashes RBI. RBI coordinates can be self-set can also be used by the periphe
LPM_RAM
- verilog 参数可设置调用模块RAM-verilog parameter can be set to call the module RAM
xiaoshu
- 基于Verilog的小数分频,带testbench，可直接modelsim仿真-Verilog-based fractional divider with testbench, modelsim simulation can be directly
DE2_Top
- 此设计是一个裸机的设计，其中包含在DE2开发板所有的引脚分配。它还包含一个与所有的对应于每个引脚的输入/输出端口的Verilog模块。这可以被用来作为一个起点上的电路板的设计。-This design is a bare-bones design containing all the pin assignments available on the DE2 board. It also contains a Verilog module with all the input/output por
Quartus-guide
- Quartus II的详细使用教程，初学verilog的可以好好看看，相信会有所帮助的-Quartus II detailed tutorial, verilog beginner can take a look, I believe will be helpful
VGA800
- 本代码用verilog语言，配合quartus里自带的fifo来简单实现vga显示屏的操作，重点在于弄清楚时序。代码中被注释的部分也可以用于彩色条纹的测试。-The code to use verilog language, with quartus in fifo comes to simply achieve vga screen operation, with emphasis on clear timing. The code portion of the notes can be te
jtag
- verilog语言编写的jtag（边界扫描模块），初学的时候可以-verilog language jtag (boundary scan module), a novice when you can look
VGAcolor
- VGA显示的Verilog程序，非常适合初学者，本程序中采用康芯的试验箱，可以改引脚锁定。-VGA display Verilog procedures, ideal for beginners, this program uses Kang core chamber, you can change the lock pin.
i2c
- iic总线编写例，可以借鉴使用，编程Verilog语言。-iic bus prepare cases, you can learn to use Verilog programming language.