搜索资源列表
RC_Engine
- 用Verilog實現的推薦系統, 用於片上系統設計-It is the Verilog source code for recommendation system. It can be used in SoC design.
vga_pic
- 利用verilog编写的程序，并且实例化了一个rom，将mif文件初始化在rom中，可以实现在vga上显示图片。文字信息等，十分实用。-Use programs written in verilog, and instantiates a rom, rom the mif file initialization, you can achieve the vga display picture. Text information, very useful.
vga256
- 利用verilog编写的可以在vga上动态显示256种颜色，自己的DIY之作。-You can use verilog prepared dynamic display 256 colors on vga, make your own DIY' s.
aadd4
- verilog 描述的超前进位加法器，速度较快，可综合-lookahead adder verilog descr iption, faster, can be integrated
adsub4
- verilog编写的可综合的加减法器 速度较快-verilog written on subtraction can be integrated faster
alu
- verilog 编写的 可综合的ALU单元 可执行加减与或非 5种运算-verilog prepared by the ALU unit can be integrated with non-executable plus or minus five kinds of computing
jiaotongdeng
- 这是基于verilog hdl的交通灯源代码，实现40秒绿灯5秒黄灯，共45秒的红灯。试过可以的。大家可以-This is based on the traffic lights verilog hdl source code, 40 seconds yellow green 5 seconds, 45 seconds, the red light. Tried possible. We can look at
shuzishizhong
- 这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。-This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.
beep
- 学习FPGA的入门程序，采用verilog语言，对时钟进行分频，控制蜂鸣器发声，可以发出七个音色，希望大家好好学习学习。-Learning FPGA entry procedures, using verilog language, clock frequency, control the buzzer sound can be issued seven tones, I hope you learn to learn.
electronic-clock
- verilog电子时钟，可以实现复位、计时、校时、闹钟等多种功能。-verilog electronic clock, you can achieve a variety of functions reset, time, school, alarm clock and so on.
20131201q_IR_gxy
- 这是调试红外的verilog代码，红外遥控输入的信息可以直接显示在数码管上-This is the infrared verilog code debugging information infrared remote control input can be displayed directly on the digital
Class_Design
- 这是我的课程设计中的一部分，用来控制1602的verilog代码，可以显示字幕-This is my part of the curriculum design, used to control the 1602 verilog code, you can display subtitles
white
- 基于verilog的VGA白屏测试程序，可在xilinx的basys2开发板上直接运行-Verilog VGA-based black and white test program can be run directly on the basys2 xilinx development board
spi_write
- spi读写驱动程序 verilog语言编写 可直接调用-spi driver verilog language literacy can directly call
altfp_log
- 浮点数 log运算模块 verilog语言编写 可直接调用-Log floating point arithmetic module can directly call verilog language
altfp_mult_abs
- 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly
altfp_matrix_mult
- 浮点数 矩阵乘法模块 verilog语言编写 可直接调用-Floating-point matrix multiplication module can directly call verilog language
quartus_works_first
- 基于verilog语言的，FPGA程序，实现可暂停的计时器与数码管显示功能，计时范围0~99秒，精度0.01秒，在EP1C3T100C8上亲测通过-Based verilog language, FPGA program implementation can pause the timer with digital display function, time range from 0 to 99 seconds, precision 0.01 seconds, measured by the
quartus_works_second
- 基于verilog语言的，FPGA程序，实现频率计与数码管显示功能，转换频率48M，精度1Hz，量程1Hz~9999Hz，有欠频率和超频率提示，精度与量程可随外部设备改变而改变，在EP1C3T100C8上亲测通过-Based verilog language, FPGA procedures to achieve frequency meter with digital display, switching frequency 48M, precision 1Hz, range 1Hz ~ 99
16QAM
- 使用verilog编写的16QAM调制解调代码，可用于quartus和ISE，因为不包含FIR，只能用于仿真，不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication