搜索资源列表
people4
- 这是我自己写的4人表决器源码,在xilinx Spartan3E 上已经调试成功,拿出来与大家分享!-that I wrote four voting machine source code, In xilinx Spartan3E debugging has been successful, with the show to share with you!
pa_ser
- 这是我自己写的4位并转串ISE代码,在xilinx Spartan3E 上已经调试成功,拿出来与大家分享!-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件,完全的代码在ALTERA的FPGA上已经通过仿真测试,保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
cfft
- 参数化FFT源代码,点数和位宽可变,内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation
uart_core_vhdlORverilog
- 串uart的vhdl,verilog,lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice versi
i2c
- I2C端口的FPGA实现,网上较多,但发现不少有问题,这个是在网上代码的基础上修改过,验证可行。-I2C port FPGA, online more, but found that many problems This is a code on the Internet on the basis of the revised test feasible.
Solutions
- FPGA代码,Designing_with_Quartus_II_Exercises_Ver11_v4_2.doc-FPGA code Designing_with_Quartus_II_Exercises_Ver1 1_v4_2.doc
LCD
- vhdl经典源代码——LCD控制,入门者必须掌握-vhdl classical source code -- LCD control, beginners must master
vga
- vhdl经典源代码——vga控制,入门者必须掌握-vhdl classical source code -- vga control, beginners must master
PS2
- vhdl经典源代码——ps2接口设计,入门者必须掌握-vhdl classical source code -- ps2 interface design, beginners must master
clock
- vhdl经典源代码——时钟设计,入门者必须掌握-vhdl classical source code -- Clock Design, beginners must master
Dial
- vhdl经典源代码——键盘接口设计,入门者必须掌握-vhdl classical source code -- the keyboard interface design, beginners must master
Frequence_Generator
- xilinx提供的频率发生器的VHDL源码,可以运行在spartan3的学习开发板上。-xilinx the frequency generator VHDL source code, spartan3 can run in the learning development board.
code
- 设计一个可编程间隔定时器,完成8253的功能,实现以下几点要求: 1、 含有3个独立的16位计数器,能够进行3个16位的独立计数。 2、 每一种计数器具有六种工作模式。 3、 能进行二进制/十进制减法计数。 4、 可作定时器或计数器。
Ham_Code_processor
- HAMMING CODE在偵錯及更正的原理實現,達到較快速的結果,浪費資源較少
rtl
- JTAG design verilog code.
OFDMRxSynchronization
- 使用FPGA設計WiMax接收機之OFDM同步硬體電路(內附VHDL code)
code
- CPLD驱动VGA显示器的VERILOG源代码.
ram
- RAM, Random-access memory,Verilog code
rom
- Read-only memory,Verilog code