搜索资源列表
RS232-for-vdhl
- RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
VHDLRS232_RS422.rar
- VHDL写的RS232和RS485通信代码,很基础的一个工具,VHDL written RS232 and RS485 communication code, it is a tool based on
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
Rs232sourcecode
- Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to
RS232
- RS232_串口通信的发送端verilog源程序代码-RS232_ serial communication sender verilog source code
PS2RS232
- 这是关于PS2和rs232串口的代码，verilog的，是深入了解串口的好的学习实例。-good code about rs232 and ps2
8051Core_RS232
- 包含了8051rs232设计的全部源码，可直接应用于sopc/FPGA设计中。-Contains all the source code 8051rs232 design can be directly applied to sopc/FPGA design.
RS232
- EP2C8Q208_Quartus_V8.0 基于FPGA实现RS232 VHDL代码-EP2C8Q208_Quartus_V8.0 FPGA-based implementation RS232 VHDL code
rs232
- 使用VERILOG 代码实现的RS232 发送功能，接收一个字符马上回送回来-The RS232 using VERILOG code sending, receiving and sent back immediately return a character
rs232
- 这是用verilog语言写的串口自收发实验的源代码，通过板子实验，采用分层模块化设计，代码大家请仔细阅读-It is written in verilog serial transceiver test from the source code through the board experiments, a stratified modular design, code, we can slowly digest
ps2-RS232
- PS2键盘字符码输出，通过FPGA控制，与pc机实现串口通信（RS232）-PS2 keyboard character code output by FPGA control, serial communication with the pc-(RS232)
RS232
- 该代码实现了根据RS232协议发送、接收数据的功能。该模块可以移植到任何使用该协议的FPGA。-The code based on RS232 protocol to send and receive data. The module can be ported to any FPGA that uses the protocol.
5-Source-code
- 5 Source code for computer ports 1- ps2 2-ps2 test 3-rs232 4-rs232 test 5-Fulladder for counter in clock divider
RS232
- 此代码已在实验板上验证，波特率9600，时钟50MHz。-This code has been verified in the experimental panel, 9600 baud, clock 50MHz.
rs232
- this is vhdl code. purpose of rs-232 connected with altera cyclone2.
RS232
- RS232与电脑串口的通信控制代码，verilog hdl代码，里面包括完整的ISE工程-RS232 and computer serial communication control code, verilog hdl code, which includes a complete ISE works
Rs232-reciever
- RS232 reciver vhdl code for RS232 EIA232-RS232 reciver vhdl code for RS232 EIA232
rs232
- rs232串口通信实验4位的串口，verilog源代码。-rs232 serial communication experiment 4 serial, verilog source code
RS232
- this code show how to use Altium to coding RS232 on FPGA-CPLD
RS232
- 串口收发代码，可设置速率，工程中已验证可用(Serial transceiver code, can set the rate, the project has been verified to be available)