Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) co

风电发电中无功补偿控制板ＣＰＬＤ程序的编写，主要配合ＤＳＰ和ＡＲＭ进行时序控制，以及PWM波的产生。-Wind power generation in the CPLD control panel reactive power compensation procedures for the preparation, mainly with the DSP and ARM timing control, and PWM wave generation.

有源电力滤波器，用于实现无功治理与谐波补偿，精度很高-Active power filter for reactive power control and harmonic compensation, high accuracy

高压链式SVG控制用FPGA的verilog程序,其中包括SPI，16路SCI同步通讯模块程序，保护自锁功能程序，基于滞环的无功功率检测和补偿策略；还包括FPGA和DSP之间通过总线方式进行数据的快速交互等；程序完整-SVG high voltage chain of verilog FPGA control procedures, including SPI, 16 road SCI synchronous communication module procedures to protect