搜索资源列表
crc
- 用Verilog编写crc校验码,包括8位,12位,16位,32位,非常实用
crc_verilog_xilinx
- 这是一个在FPGA上实现CRC算法的程序,包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。
trunk-hdlc.rar
- 高级链路层协议的实现,vhdl,fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
crcm
- crc 校验,vhdl源码,经仿真能正常运行,供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
CRC16bits
- 16bit crc encoder ande demo
crc
- CRC-16 VHDL Source Code
crc_verilog_xilinx
- CRC,对于研究通信的有重要意义.利用VERILOG实现8位,16位等CRC原理,-CRC, the study of communication are important. VERILOG to achieve the use of 8, 16, such as CRC principle,
CRC_16
- crc16的串行和并行写法,而且有详细的测试文件-Serial and parallel crc16 written, and detailed test documents
crcvhdl
- crc-vhdl冗余码的vhdl源码,这是16位的crc-crc-vhdl vhdl source code redundancy, which is 16-bit crc
PCK_CRC16_D1
- CRC源代码,VHDL文件,可供参考,16位的-CRC source code, VHDL files, for reference, 16-bit
CRC
- Cyclic redundancy check code (16-bit) Very good code verified code
CRC
- 一個CRC-12計算的串入式電路並下載至FPGA電路板-FPGA CRC-16
Perl_for_CRC
- Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redu
CRC-Parallel-Computation
- 用软件实现CRC校验码计算很难满足高速数据通信的要求, 基于硬件的实现方法中, 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础, 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based
CRC.C
- 下面以最常用的CRC-16为例来说明其生成过程。 CRC-16码由两个字节构成,在开始时CRC寄存器的每一位都预置为1,然后把CRC寄存器与8-bit的数据进行异或(异或:二进制运算 相同为0,不同为1;0^0=0 0^1=1 1^0=1 1^1=0), 之后对CRC寄存器从高到低进行移位,在最高位(MSB)的位置补零,而最低位(LSB,移位后已经被移出CRC寄存器)如果为1,则把寄存器与预定义的多项式码进行异或,否则如果LSB为零,则无需进行异或。重复上述的由高至低的移位8
CRC
- CRC校验参考设计Verilog代码,crc8,16,32bit- crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input.
fast-crc.tar
- crc-16-code for check redundancy code fast in 16 bit- in parallel and serial architecture-crc-16-code for check redundancy code fast in 16 bit- in parallel and serial architecture
c_crc16
- CRC 16 development code
crc_verilog_xilinx
- 包括下面文档: readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. cr
CRC
- CRC32:polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) * data width: 8 CRC16:polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) * data width: 8