搜索资源列表
309361_88321a222b5ae22c
- DCT 图像处理 基于VHDL语言 简单可行-DCT image processing language based on VHDL
dwt2d
- discrete wavelet transform - 2d
DCT
- Discrete Cosine Transform
DCT_IDCT
- H264/AVS中的离散余弦变换DCT以及反离散余弦变换IDCT的Verilog代码-H264/AVS the discrete cosine transform and inverse discrete cosine transform DCT IDCT of Verilog code
JPEG_WEBINAR
- JPEG DCT C 代码，可在Catapult下生成VHDL -JPEG DCT C code for VHDL generation in Catapult
dctidct
- dct and idct code for verilog
DCT8_final
- 二维dct算法的fpga实现及验证，采用VHDL语言编写。-2D-dctThe FPGA realizing algorithm
2dDCT
- 二维dct算法的fpga实现及验证,采用VHDL语言编写。-2D-dct The FPGA realizing algorithm
s22_DCT
- 这是一个DCT变换的VERILOG代码，欢迎下载-This is a code of DCT transformation in verilog ,welcome to download!
OneD_DCT8
- 一维DCT变换，使用Verilog ＨＤＬ语言实现。有ＳＹｎｐｌｉｆｙ编译脚本-One-dimensional DCT, using the Verilog HDL language to achieve. The SYnplify compiled scr ipt
Ttwo_d_dct_sew
- 二维DCT变换，采用查找表的方法实现算法，分别通过列变换，，再通过行变换，通过加法器乘法器和流水线技术得出更快的结果！ -2D DCT algorithm using look-up table method, respectively, by column transform, and then transform through the line faster results obtained by the adder multipliers and pipelining techniq
IDCTTzipm
- 改进的DCT算法设计，，veriloghdl实现 -Improve the DCT algorithm design,, veriloghdl to achieve
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
IQIT
- Inverse quantization and DCT for h.264 in verilog
shift_arr
- This contains the shift array which can be used in 2D DCT with help of 2 1D DCTs.
wallace
- wallacw tree multiplier code in vhdl language mainy used for the multiplications in the image [processing of both dct and dwrt applications-wallacw tree multiplier code in vhdl language mainy used for the multiplications in the image [processing of
INT_DCT
- Verilog HDL语言实现的整数DCT变换模块。其中包括一维和两维的DCT变换模块各一个。该模块都通过硬件仿真以及FPGA实现后的测试，均满足预期的DCT变换功能。-Integer DCT transfer module with Verilog HDL format. The package includes one 1-D and one 2-D DCT transfer module, which all pass simulation and FPGA evaluation.
fpga-jpeg
- 包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程-Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project
DCT_IP_Testbench
- 一个DCT变换的完整IP，基于Verilog编写，同时包括完成的testbench，方便模块的仿真和测试。-DCT transform a complete IP, based on Verilog prepared, including both complete testbench, convenient module simulation and testing.
High-Throughput-DA-Based-DCT-With-High-Accuracy.r
- This is Discrete wavelet transform based IEEE object...this is developed in vhdl