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用FPGA实现DDS信号发生及用MODELSIM仿真
- 该工程是用verilog编写,FPGA内部产生ROM及ADD加法器。ROM中存正弦波信号。文件夹中还包含modelsim仿真。
accumulator.rar
- 实现累加器的verilog源码,广泛应用在通信电路设计中,The realization of accumulator Verilog source, widely used in communication circuit design
DDS
- 用Verilog编写的DDS逻辑,很好地实现了DDS功能,可以产生各种频率的正弦波。-DDS which was write by Verilog。
EDA.rar
- 这里边有EDA设计常用模块的源代码,FFT,DDS PS2_keyboard,VGA等,有学FPGA的就参考一下吧,Here the design of commonly used modules have EDA source code, FFT, DDS PS2_keyboard, VGA and so on, have places on the FPGA reference yourself
AD9954_test
- AD公司DDS芯片AD9954的Verilog测试程序-VerilogHDL test program of DDS chip--AD9954 ,producted by AD company
MyDDS
- 利用查找表法编写的DDS的verilog程序,节省了利用IP核实现需要的资源,软件为ISE,-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
DDS
- 这个是我自己用VHDL语言写的两相数字信号发生器程序 D/A用的是DAC904-This is for my own use VHDL, written procedures for two-phase digital signal generator D/A using a DAC904
cordic
- 该程序使用Verilog语言,可以生成dds正余弦信号-The program uses the Verilog language, can generate sine and cosine signals dds
ddsfinal1
- verilog语言实现的dds代码,并行通信,生成四种波形,大赛编写的代码,modelsim仿真-verilog language dds code,modelsim debug
dds
- 采用verlog编写的tlc5615驱动程序,并利用了rom核实现了dds功能-Using verlog written tlc5615 driver, and use the rom-core functions to achieve a dds
Verilog-dds
- 用Verilog实现的DDS,直接频率合成器,相位可调。-Verilog DDS generator
DDS-Verilog-design-and-simulation
- DDS的Verilog设计及QuartusⅡ与Matlab联合仿真 -dds s verilog simulation dds s verilog simulation dds s verilog simulation dds s verilog simulation
DDS-VERILOG
- DDS的信号发生器verilog代码 可直接用于编程 已经测试-Verilog code of the DDS signal generator which can be used directly in the programming has been tested
DDS-MY-WORK-1
- FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog
DDS-verilog
- DDS是直接数字式频率合成器(Direct Digital Synthesizer)的英文缩写,是一项关键的数字化技术。与传统的频率合成器相比,DDS具有低成本、低功耗、高分辨率和快速转换时间等优点,广泛使用在电信与电子仪器领域,是实现设备全数字化的一个关键技术。文件写了一个DDS的例程,并编写了TB文件。-DDS is a direct digital synthesizer (Direct Digital Synthesizer) of the English abbreviation, i
dds(1)
- 基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
DDS波形发生器
- DDS波形生成器verilog语言书写(FPGA型号cy4以上)(DDS generate verilog)
dds
- 基于DDS的信号源设计(包括三角波、正弦波、方波)(Design of signal source based on DDS)
DDS的VERILOG原代码
- 实现了DDS的verilog源代码,可以使用(ajhsjdhjkshfjhfsjkjksa)
dds_PIO
- 利用QSYS中自带的PIO接口实现DDS模块(Using the PIO interface in QSYS to implement the DDS module)