搜索资源列表
lcd_driver_4bit
- it is a 4-bit lcd driver written in verilog .it will work on spartan 3 xilini devices.
4_31
- 这是一个交织器/解交织器的FPGA实现，虽然交织器的功能简单，但是其实现比较复杂-This is an interleaver/de-interleaver to achieve the FPGA, although the function of interleaver simple, but its more complicated to achieve
DivFreq
- diviseur de frequence en VHDL
DE2Project_restored
- 一个在全国电子设计大赛上的基于DE II的实际工程-One in the National Electronic Design Competition on the DE II Based on the actual project
Signal
- yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.-Used VerilogHDL to make a frequency builder.
DE2_SD_Card_Audio
- DE2_SD_Card_Audio是基于DE II的音频从SD卡读入的VHDL语言程序-DE II on the basis of DE2_SD_Card_Audio audio from the SD card is read into the VHDL Language Program
DE-II-I2C
- 基于DE II实验平台，读取音频信号的I2C总线控制程序- based on the DE II experimental platform, the audio signal read I2C bus control procedures
contador_n_bits
- n-bits counter vhdl with testbench. contador de nbits en vhdl con simulacion.
divisor_n_bits_sin_restauracion
- vhdl divisor of n-bits without restaurecion metod. divisor de nbits en vhdl sin restauracion. con testbench.
DE2_70_NIOS_14_ssram
- Altera公司DE-70开发板中16位SDRAM的32位用法，纯硬件实现哦-Altera DE-70 16MX16SDRAM =>32bits
rstk-0.7.tar
- archivo reed solom para utilizar en decodificacion de television digital esta en vhdl
Digita_mediante_VHDL
- practica de ejercicios de vhdl
UART1X
- code spimaster a de transmissor receptor
ENT6
- 加法计数器的VHDL工程，程序，仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU
fdivide1
- 分频器的VHDL程序，完整的建立工程，编译，功能功能仿真，验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng
moore
- mooor状态机的VHDL程序，代码，状态机，关键是分析各个状态之间的切换-mooor zhuangtaiji zhuagtaiji guanjianshi gege zhuangtai zhijian de qiehuan
contador_0a7
- contador de 0 a 7 que se reinicia
sumadores
- Carry look ahead, sumador con acarreo de 32 bits
DE2_UserManual
- DE-2 开发板的的用户手册，可以帮助理解适用DE-2 开发板-DE-2 development board user manual, can help understand the application development board DE-2
新建文件夹
- Verilog语音，FPGA产生DE，HS，VE信号()