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xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
H.264_Technical_Primer
- 广播头端的FPGA的设计指导 帮助你顺利完成DVB的FPGA设计，-Broadcast head-end FPGA design guide to help you successfully complete the DVB' s FPGA design,
Analysis-Of-The-Dvb-Common-Scrambling-Algorithm.r
- Analysis of the DVB Common Scrambling Algorithm (DVB-CSA) on FPGA implementation. Performance and Security.