搜索资源列表
AEScoremodules
- AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest
bch_encoder_decoder
- bch encoder+decoder 源代码，Flash控制器，通讯都需要用到哦
Manchester.rar
- 曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档,Manchester Encoder-Decoder
manchester-decoder-encoder
- Manchester Encoder - Decoder-Manchester Encoder- Decoder
encoder
- vhdl的七段译码器-The Seven-Segment Decoder VHDL
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
MAC_MP3_Hardware
- MPeg audio encoder/decoder codes
Audio_Bit_Counter
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Audio_In_Deserializer
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Audio_Out_Serializer
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Avalon_Audio
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Clock_Edge
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
SYNC_FIFO
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
encoderdecoder
- this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year proj
viterbi
- viterbi decoder with convolutional encoder
EnergyEfficientVLSIArchitectureforLinearTurboEqua
- Energy efficient for turbo encoder decoder
hdbn_latest.tar
- This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703.
viterbi
- verilog code for viterbi encoder and decoder
rs_dec_enc_latest.tar
- RS encoder decoder on vhdl
Bch15_7
- BCH ENCODER DECODER -BCH ENCODER DECODER