搜索资源列表
coder_counter
- 增量式光电编码器计数器的FPGA实现程序,verilog3段式FSM,异步加载.-Incremental Optical Encoder counter program FPGA implementation, verilog3 struts FSM, asynchronous load.
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
chengxu
- 一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
vhdl
- 最高优先级编码器和直流电机控制器,供初学者学习使用，方便快捷，有很强的参考价值-The highest priority encoder and DC motor controller, for beginners learning to use, convenient and has a strong reference value
crcm
- crc 校验，vhdl源码，经仿真能正常运行，供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
CRC16bits
- 16bit crc encoder ande demo
s3esk_rotary_encoder_interface
- Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Ro
A-law_enc
- A-law Encoder (VHDL)
RS
- reed selemon encoder vhdl code
vhdl-JPEG-enc
- JPEG Encoder,Here is a quite detailed low level design document for the Core: Low Level Design Document
Convolutionalencoder
- 应用VHDL语言实现的卷积编码器的应用程序-Application of VHDL language implementation of the convolutional encoder applications
MAC_MP3_Hardware
- MPeg audio encoder/decoder codes
OpCtrl
- 步进电机的转动控制程序,可用于变速,和编码器混合使用-Stepper motor rotation control program can be used for variable speed, and mixed use encoder
RS_ENCODER
- DVBC RS编码,标准TS流输入输出接口!-DVBC RS encoder
vhdl
- ldpc编码的vhdl的实现，一种802.13的方式-ldpc coding vhdl implementation, a 802.13 a way
my_code
- 编码器和译码器，Verilog实现，有具体实验说明文档。-Encoder and decoder, Verilog realization of a specific experiment documentation.
RS
- RS编码器的VHDL源程序,程序有点大，不过能用。-RS encoder VHDL source code, program a little big, but can be used.
123
- 将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained s
ldpc_encoder_802_3an_latest.tar
- LDPC encoder in verilog
FPGA-convolutions-encoder
- 卷积码是数字通信中很重要的一种差错控制编码 具有很好的性能,用硬件的形式描述具有速度快，便于修改的优点，通过该种方法设，计的编码器经测试运行可靠正确。-Convolutional codes are very important in digital communication error control coding with a good performance, with the descr iption of the hardware in the form of a fast, eas