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  1. tAtan2Cordic.rar

    1下载:
  2. 是codic算法实现atan的C程序,包括定点和浮点程序,已经通过验证。,Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-21
    • 文件大小:3.16kb
    • 提供者:张堃
  1. 16bitFFTFPGA

    0下载:
  2. 16位定点FFT-DSP的FPGA实现(相关代码和使用说明)-16-bit fixed-point FFT-DSP implementation of the FPGA (the relevant codes and instructions)
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-16
    • 文件大小:3.57mb
    • 提供者:tanghongwu
  1. adaptive_lms_equalizer_latest.tar

    0下载:
  2. In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:13.54kb
    • 提供者:Arun
  1. chufaqichengxu

    0下载:
  2. 除法器程序,除法器模块,定点数除法的相关代码。-Divider procedures, divider module, the related fixed-point code division.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:382.63kb
    • 提供者:jiachen
  1. fix2float_signed

    0下载:
  2. VHDL语言,有符号定点数转化为浮点数,Pavle Belanovic教授编写-Conversion from signed fixed-point to floating-point representation
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:3.06kb
    • 提供者:刘畅
  1. arraymultiplier

    0下载:
  2. vhdl code,about arraymultiplier,fixed point
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:876byte
    • 提供者:esther
  1. float_fixnumber

    0下载:
  2. 将15位(1,5,9)格式的浮点数转换成18位的定点数-To 15 (1,5,9) floating-point format into 18 fixed points
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:365.57kb
    • 提供者:陈晓
  1. vhdl-floating-pt

    0下载:
  2. code for fixed & floating point-code for fixed & floating point........
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:19.36kb
    • 提供者:nagesh
  1. cordic

    1下载:
  2. we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentia
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:1.77kb
    • 提供者:Nihel Neji
  1. Simulink-to-VHDL-Route

    0下载:
  2. This paper presents the way of speeding up the route from the oretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-24
    • 文件大小:144.46kb
    • 提供者:jack
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