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dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
jktrig
- 时序逻辑电路中jk触发器的设计，用vhdl语言编写。-Jk flip-flops in sequential logic circuit design, using vhdl language.
INC_DEC_GEN
- This an Generic Incrementer - Decrementer made wid flip-flops in VHDL-This is an Generic Incrementer - Decrementer made wid flip-flops in VHDL
counter
- -- Mod-16 Counter using JK Flip-flops -- Structural descr iption of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal
jk
- Different vhdl programs are like jk flip flops, conters,prbs generator,multiplier,8-bit adder are uploaded
project6_source
- VHDL D_Flip-Flops D Flip-Flop P/C layout and results of verification.
lab2
- D-type storage elements The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops. Write a VHDL file that instantiates the th
Dlatch3
- 基于VHDL的触发器设计。 由一个电平触发的D触发器构成的上下边沿触发器。-Trigger-based VHDL design. Consists of a level-triggered D flip-flops up and down the edge of the trigger.
8a
- 2 Flip Flops in VHDL