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  1. arith_lib_cadence

    0下载:
  2. Cadence的VHDL运算库包,实现求方根,平方你是不是以前不知道怎么弄.哈哈.-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:80.77kb
    • 提供者:喻袁洲
  1. xlinx_ise_excd1_edk_flash_program

    0下载:
  2. 这是一个网友向我提问如何实现EXCD1开发板的FLASH管理,我编写的一个Xilinx的EDK设计包括设计步骤说明,没有经过实际测试,希望在实际使用中有问题的网友与我讨论。谢谢!-This is a friends asked me how EXCD1 development board FLASH management, I prepared a Xilinx s EDK design and including the design steps that, without actual te
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-21
    • 文件大小:6.23mb
    • 提供者:YongZhiLi
  1. EDA

    0下载:
  2. 这个是关于如何用VHDL语言实现微波炉功能的一片论文,大家感兴趣的话,可以看看。-This is about how to use VHDL language features a microwave oven paper, we are interested, you can see.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:86.74kb
    • 提供者:李健
  1. Verilog-HDL

    0下载:
  2. a dvan let go look ing down hello how are you today
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-18
    • 文件大小:4.81mb
    • 提供者:nghia
  1. AssignmentP6

    1下载:
  2. 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
  3. 所属分类:VHDL编程

    • 发布日期:2015-12-10
    • 文件大小:113.18kb
    • 提供者:魏攸
  1. 1

    0下载:
  2. 将“How are you”通过LCD显示出来,并能够在you前面换行-display how are you on the LCD
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:1.37kb
    • 提供者:王丽华
  1. ddslabview

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  2. The reference design and example presented in this article illustrates how you can add a DDS (direct digital synthesis) waveform generator to your LabVIEW FPGA based applicationThe examples for this article are contained in a LabVIEW 8.5.1 project.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-13
    • 文件大小:3.12mb
    • 提供者:charlysed
  1. modulesim

    0下载:
  2. 学习EDA的一款非常好的软件modulesim的资料文档,详细介绍了该款软件是如何用的。这里有3份材料,读完之后,就会掌握这款软件了-Learn the EDA a very good software modulesim of the information document, detailing how to use the software to. There are 3 materials, after reading it, you will master this software
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-22
    • 文件大小:10.26mb
    • 提供者:
  1. descode

    0下载:
  2. Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorit
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:5.32kb
    • 提供者:akram
  1. tcdg

    0下载:
  2. Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorit
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:5.32kb
    • 提供者:akram
  1. test-des

    0下载:
  2. Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorit
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:5.32kb
    • 提供者:akram
  1. FPGA_AND_ASIC

    0下载:
  2. 首先要知道自己在干什么?数字电路(fpga/asic)设计就是逻辑电路的实现,这样子说太窄了,因为asic还有不少是模拟的,呵呵。我们这里只讨论数字电路设计。实际上就是如何把我们从课堂上学到的逻辑电路使用原理图(很少有人用这个拉),或者硬件描述语言(Verilog/VHDL)来实现,或许你觉得这太简单了,其实再复杂的设计也就是用逻辑门电路搭起来的。你学习逻辑电路的时候或许会为卡拉图,触发器状态推倒公式而感到迷惑,但是其实有一点可以放心的是,实际设计中只要求你懂得接口时序和功能就可以了,用不着那么
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-12-15
    • 文件大小:19kb
    • 提供者:吕攀攀
  1. 8QAM-matlab程序

    0下载:
  2. QAM编程 自适应QAM必须的程序段,相信我,没错的,哈哈哈哈哈哈。(qam english ha he hello hi how are you i am fine thank you and you da ming tofu koungfu)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-05-03
    • 文件大小:9kb
    • 提供者:iermeng
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