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crc
- CRC-16 VHDL Source Code
hdbn_latest.tar
- This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703.
itu-t81
- itu coding haffman etc-itu coding haffman etc.......
DE2_TV_PAL_TO_RGB_DE2
- 从adv7181b译码itu-656格式的YUV 4:2:2信号,调试过的能在DE2上运行的pal转rgb-decode itu-656 4:2:2 YUV format signal from adv7181b
hdbn_latest.tar
- This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703.
itu656
- convert pal to itu-656
mkjpeg.tar
- 用FPGA实现的JPEG编码器,可以直接使用,内含完成说明文档,经过验证无误。-• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color images only (3 components, RGB 24 or 16 bit, YUV input) • T
bt1120p_gen
- bt1120时序生成,verilog程序,1920x1080p60分辨率-synchronized video timing generation itu bt1120 within verilog program, 1920x1080p60 resolution
DE2_TV
- 本代码为Altera DE2开发板例程源码,(FPGA:EP2C35F672C6)quartus II 9.0以上可以编译(随板源码为7.2以下版本,在9.0以上版本编译会报错)。本代码实现一个音视频播放器TV_BOX。-This demonstration plays video and audio input a DVD player using the VGA output and audio CODEC on the DE2 board. There are two major bl
bt656_timing_analysis
- BT656信号分析参考规格书,对分析bt656信号非常有帮助-The video standard ITU-R.656 timing analysis
hdbn
- This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703. Note: HDB2 and
DE2_115_TV
- 这个设计范例使用 DE2-115 上的 VGA 输出、音频编解码芯片以及 TV 解码芯片( U6)播放 来自 DVD 播放器输出的视频和音频信号。 图 6-1 给出了设计的原理框图。系统主要由两个 模块组成,它们是 I2C_AV_Config 以及 TV_to_VGA 模块。 TV_to_VGA 模块由 ITU-R 656 解 码器, SDRAM 帧缓冲器, YUV422 转 YUV444, YcrCb 转 RGB 以及 VGA 控制器组成。 从 图中还可以看出,设计使用了 TV
e1-framer
- e1 framer / de-framer based on itu-t standards state machine using GRAY CODE (or trying to use GRAY CODE
crc16_d8
- 此代码采用Verilog语言实现8位CRC校验功能,采用CRC-ITU标准制定的CRC16校验-This code USES the Verilog language function of eight CRC check the CRC- ITU CRC16 calibration standards
cavlc-decode
- 兼容ITU-T H.264(05/2003),但它不计算nC和存储TotalCoeff, 你需要在这个核心之外添加一个nc_decoder-Compatible with ITU-T H.264 (05/2003), but it do not calculate nC and store TotalCoeff, you need to add a nC_decoder outside this core