搜索资源列表
jkchu
- jk触发器，自己尝试编辑的，用状态机实现，可以
djkrs
- d,jk,rs触发器的vhdl语言实现，简单明了
vhdl
- 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
jk_ff
- 这是我自己写的一个关于JK触发器的VERILOG 程序。-This is one I wrote it myself on the JK flip-flop process of VERILOG.
jkff
- JK flip-flop is implemented using VHDL
vhdl_jk
- 本程序通过使用vhdl语言描述JK触发器，实现了JK触发器的四个工作状态，进而我们可以将其应用到其他使用JK触发器的电路中-The procedure by using vhdl language to describe the JK flip-flop, JK flip-flop realized the four working state, then we can apply it to others using the JK flip-flop circuit
jktrig
- 时序逻辑电路中jk触发器的设计，用vhdl语言编写。-Jk flip-flops in sequential logic circuit design, using vhdl language.
trigger
- D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
JK
- 一个JK触发器 虽然比较简单 但或许会对你有用 里面代码跟仿真都有-FPGA
jk
- 触发器设计范例，JK触发器的VHDL实现-Trigger for example, JK flip-flop of VHDL implementation
JK
- JK触发器的功能实现，采用VHDL编程，可以下载到FPGA中进行演示-JK flip-flop implementation of function, using VHDL programming, you can download a presentation to the FPGA,
jk
- Different vhdl programs are like jk flip flops, conters,prbs generator,multiplier,8-bit adder are uploaded
JK
- 使用jk触发器来实现CMI码的编译码，延时小，操作方便-Using jk flip-flop to achieve the CMI code encoding and decoding, the delay is small, easy to operate
jk
- 基于quartus2的jk触发器设计，内含源码和仿真图-Jk flip-flop design based on the quartus2, containing source code and simulation diagram
vhdl-code-for-jk-flip-flop
- vhdl program of jk flip flop. positive edge triggerd. the test bench is also available with the code. a simple program to start with vhdl
JK
- 带复位端、置位端、延迟为15ns的响应CP下降沿的JK触发器-With reset terminal, set end delay the 15ns CP' s response to the falling edge of the JK flip-flop
JK-flip-flop
- 带有异步置位复位端的上升沿触发的JK触发器，使用VHDL语言实现的-Asynchronous reset terminal set with rising edge triggered JK flip-flop, the use of VHDL language
jk-filpflop
- 这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的-This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met
JK-flipflop_vhdl
- FOR LEARNING PURPOSE... VHDL CODE OF JK FLIPFLOP