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ARMloadFPGA(3)
- ARM加载FPGA.实现ARM和FPGA之间的正确通信-ARM LOAD FPGA ,TO LET THE ARM AND FPGA TO WORK
flash_loader_II_for_2c20
- FLASH_LOADERII是cpld配置fpga的程序。运行在quartus60环境下。-Fpga configuration FLASH_LOADERII is cpld procedures. Run on quartus60 environment.
daima
- 用VHDL语言设计一个8位加法器: 在八位加法器代码一中:加法器是由两个4位二进制加法器U1和U2组成的8位加法器逻辑电路,其中U1用来装载8位加法器中两个加数的低4位,而U2则用来装载高4位。在设计4位加法器时,定义输入信号量CIN、A、B以及输出信号量S、Cout。定义信号量SINT/AA/BB,将加数A和0并置后赋给AA,加数B和0并置后赋给BB,形成5位二进制数,这是为在做加法时发生溢出所做的处理,然后将加数AA与BB以及进位Cin相加赋给SINT,并将SINT的低4位赋给加数和S输
s7enable_send0x55_UART_9600
- 最简单的UART发送程序,vhdl编写,系统时钟40M,波特率9600,外Load有效(一个高脉冲)即向PC发送一个字节0X-UART to send the simplest procedures, vhdl prepared, the system clock 40M, baud rate 9600, outside the Load effective (a high-pulse) to the PC sends a byte 0X55
unishift
- An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
Traffic_Light_Controller
- 该控制器在设计上控制了一个繁忙的高速公路(高速路的红绿灯) 相交一岔路(SRD)等具有相对较轻的交通负荷。图1显示 在交通灯的位置。在十字路口传感器检测汽车的存在 在公路上和岔路。该图意味着,无论是公路和副作用 道路提供每个方向的交通单一车道。这两个普通的道路(红, 黄,绿)信号灯。交集装有一个传感器。-The controller to be designed controls the traffic lights of a busy highway (HWY) inter
processor
- processor design istruction load pipeline ,hazard
project_E05_124
- 8 bit computer. Here fore instruction can load to the program counter.Code is written using Xlinx ISE and tested using test bench. Four instructions are load, move, add and sub.
VHDLstudy
- 近期学习程序小结,对初学者比较有帮助,包括:四D触发器:74175 用状态机实现的计数器 简单的12位寄存器 通用寄存器 移位寄存器:74164 带load、clr等功能的寄存器 带三态输出的8位D寄存器:74374等 -Summary of recent learning process, more helpful for beginners, including: four D flip-flop: 74 175 with a simple state machine im
virtex-5fpgaconfigurationuserguide
- virtex-5 上电加载程序的时序的详细说明,包括bin文件的加载时序-virtex-5 on the power loader timing of the detailed descr iption, including the bin file load timing
slice
- A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually inter
PWM_GENERATOR
- PWM, or Pulse Width Modulation, is a method of controlling the amount of power to a load without having to dissipate any power in the load driver.
XtreamWay-update
- 本次只需要升级交换板SF2300上的软件版本,升级完成并重启后SF2300会自动加载更新后的应用承载板AC2240软件 在SF2300的应用维护模式appadmin下更新xway_om.zip, 在SF2300的管理维护模式OMadmin下更新xway_node.zip, xw_rpc.tar.gz是用于x86刀片服务器对FPGA卡进行RPC调用的软件包 软件更新方法、XtreamWay交换协议、FPGA远程调用方法等可参考附件中的说明文档 -
Microprocessor_load_store
- Implementation of a simple microprocessor having a load-store architecture.
debounce
- push button program that take 20ms afther that it load data
behavioral_counter
- -- This example implements a behavioral counter with load, clear, and up/down features. -- It has not been optimized for a particular device architecture, so performance may vary. Altera recommends using the lpm_counter function to implement a co
decrypt_controll
- controller for fast_aes128. Sends start and load pulses at a lower clock than main_clk.
cnt10
- 设计带有异步复位、同步计数使能和可预置型的十进制计数器。 具有5个输入端口(CLK、RST、EN、LOAD、DATA)。CLK输入时钟信号;RST起异步复位作用,RST=0,复位;EN是时钟使能,EN=1,允许加载或计数;LOAD是数据加载控制,LOAD=0,向内部寄存器加载数据;DATA是4位并行加载的数据。有两个输出端口(DOUT和COUT)。DOUT的位宽为4,输出计数值,从0到9;COUT是输出进位标志,位宽为1,每当DOUT为9时输出一个高电平脉冲 -Designed with
Interactive-state-machine
- 交互状态机建模,交互状态机能够使用通过公共寄存器通信的独立的a l w a y s语句进行描述。 示的两个交互进程的状态图, T X是一个发送器, M P是一个微处理器。如果进程T X不忙,进 程M P将要发送的数据放置在数据总线上,然后向进程T X发送信号L o a d T X,通知其装载数据 并开始发送数据。进程T X在数据传送期间设置T X B u s y表明其处于忙状态,不能从进程M P接 收任何进一步的数据。-Interactive state machine mode
VHDL
- ENTITY FREQ_T IS PORT(CLK:IN STD_LOGIC FREQ_EN:OUT STD_LOGIC CNT_CLR:OUT STD_LOGIC Load:OUT STD_LOGIC) END FREQ_T