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目前以太网PHY芯片是通过总线MDC/MDIO
- 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理,At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA
i2c
- This code implements the control of the i2c bus with a MC68000 type interface. It is modeled from the M-bus component in certain Motorola uC. The I2C control is done in the component i2c_control and the uC interface is implemented in the component u
LIP1732CORE_system_mbus_arbiter
- System Verilog M bus arbiter module
Interactive-state-machine
- 交互状态机建模，交互状态机能够使用通过公共寄存器通信的独立的a l w a y s语句进行描述。 示的两个交互进程的状态图， T X是一个发送器， M P是一个微处理器。如果进程T X不忙，进 程M P将要发送的数据放置在数据总线上，然后向进程T X发送信号L o a d T X，通知其装载数据 并开始发送数据。进程T X在数据传送期间设置T X B u s y表明其处于忙状态，不能从进程M P接 收任何进一步的数据。-Interactive state machine mode
pci_to_wb_latest[1].tar
- 该ip核实现了容量为16MB的、双字、可寻址存储镜像与wishbone总线的连接-This core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the minimum which is required by the PCI specification (and I m really t