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uriscram
- RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write= 1 则mem(conv_integer(address))<=datain.
vga_hex_disp.rar
- 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。,The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compilin
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
mem_test
- 简单的存储器内核测试，已经验证通过，VLOGER编写-Simple memory core testing, has been adopted to verify, VLOGER prepared
LIP2908CORE_membist
- Mem bist Verilog Module
VGA-Controller
- FPGA do vga display controller. achieve include: fifo mem, vga core, rgb controller,
cpu
- 设计一个简化的处理器（字长8位），并使其与内存MEM连接，协调工作。用VHDL以RTL风格描述。该处理器当前执行的指令存放在指令寄存器IR中。处理器的指令仅算逻指令和访问内存指令）。-Design a simplified processor (8-bit word length), and connect it with the memory MEM, and coordination. Described with VHDL in RTL style. The processor is c
mem
- verilog硬件描述语言开发的memory-verilog hardware descr iption language developed memory
mem-opt_final
- memory optimisation cache memory, RAM,SRAM, main memory related doc and ppt attached
mem_test
- ROM存储器的Verilog测试程序，希望对大家有帮助！-ROM memory of the Verilog test program, we want to help!
testbenchHw9-Parts-Mem
- // EE 361 Hw 9 Testbench for sequential circuit Parts // * 128 word data memory and IO
VHDL-for-Datapath
- MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg
mem
- This my version of a memory module that can be used in a digital device to store the filter coefficients.-This is my version of a memory module that can be used in a digital device to store the filter coefficients.
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11
mem
- 一种用于测试SRAM阵列的MARCH-C算法；使用Verilog语言描述，包括SRAM模块、MRACH-C算法还有testbench-An algorithm for MARCH-C test SRAM array using Verilog language descr iption, including SRAM module, MRACH-C algorithms as well as testbench
SRC
- 流水线CPU的verilog实现，包含id，if，ex，mem等部分的源码-an implementation of Pipelined CPU in verilog
pg058-blk-mem-gen
- blockram的手册，适合开发者使用是xilinx的(Blockram manual, suitable for developers to use, is Xilinx)
D_cache
- 数据缓存的模块设计，连接流水线mem模块。(The module of data cache is designed to connect the pipeline MEM module.)