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Verilog HDL使用中该注意的问题及一些模块代码
- cpu仿真,提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
OpenMIPS
- 《自己动手做CPU》书后源码 包含各章节实例 分节使用(source code of mips CPU)
soc_sram_func
- 利用verilog编写的32位 MIPS指令集CPU,sram接口,已上板验证(The 32 bit MIPS instruction set CPU, SRAM interface written by Verilog has been verified on board.)
mips-cpu-master
- CPU设计,已通过模拟,有需要的自行下载吧(CPU design has been simulated)