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modelsim6.2b
- 使用Modelsim进行仿真,包括前仿真,与后仿真,使用Quartus 调用Modelsim进行仿真-Using Modelsim simulation, including the former emulation, and after the simulation, the simulation using Quartus call Modelsim
spi_master
- 用VHDL编写的一个SPI主机程序,SPI模块采用最常用的模式0方式(即CPOL=0,CPHA=0)通信。文件内含测试文档,已在Modelsim6.5上测试通过,可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
UART-and-FPGA
- 基于FPGA的UART通信控制器 设计与实现持。用到modelsim6.1f环境模拟。-UART communication controller based on FPGA Design and Implementation of hold. Used modelsim6.1f environment simulation.
StopWatch
- 在Modelsim6.3c中编码,与Virtex-II Pro开发板连接实现秒表功能-In Modelsim6.3c encoding, and Virtex-II Pro development board to achieve a stopwatch function
fifo
- 在Modelsim6.3c中实现同步fifo-In Modelsim6.3c achieve synchronous fifo
Music_Player
- 基于Verilog的音乐播放器程序,在Modelsim6.5上仿真通过并可以在开发板上运行-Verilog-based music player program, in Modelsim6.5 through simulation and can be run on the development board
Counter
- best simple counter for verilog modelsim6.5