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Comparators_16B
- verilog 实现 优化的16位比较器 可以输出大于，小于，等于。模块化设计，可扩展为32位-Verilog achieve optimization of 16 compared with the output can be greater than, less than, equal to. Modular design, which can be expanded to 32
CompilerOptimizations
- To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level o
vhdl
- ：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。-: A Shanghai taxi meter area for example, the use of Veri
ctrller
- 本代码是控制SDRAM的VHDL代码，几经优化现已趋近完美，里面主要用状态机实现，现封装为entity，便于调用模块-This code is to control the SDRAM of the VHDL code, optimization has been several times closer to perfection, which is mainly used to achieve a state machine is encapsulated entity, easy to c
lowpowerfir
- This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the syst
TDvedynausermanual
- ve-DYNA® 为用户提供了车辆动力学、车辆非线性行为的可配置仿真模型。用户根据自己的工程问题选择合适的车型（轿车，货车，拖车）和适当的版本（低级，标准，高级）就能实现不同的应用。用户基于模型就能开发自己的控制算法或者部件，然后通过离线仿真和硬件在回路仿真来进行检验和验证。只需要进行鼠标键盘的操作，就可以对种种的动力学问题进行分析，比如悬架动力学，车辆动力性或操纵稳定性。这样 就 能够减少昂贵而且费时甚至是危险的实车试验。可以在无人监控的情况下完成整个的测试、优化和系统验证 。本文为v
DATA_CONV_encode
- 绍了FPGA的优化技术： 速度优化、功耗优化、面积优化，并且以实例来说明。-Introduce the optimization of FPGA technology: speed optimization, power optimization, area optimization, and examples to illustrate.
FSM
- 文章介绍的状态机的优化写法，并给出经典实例。使读者更清楚的明了FPGA中状态机的优点，以便工程中的使用。-This paper introduces the optimization of state machines written, and gives the classic example. So that readers understand more clearly the advantages of FPGA in the state machine to the project u
senior-FPGA-design-tech_Xilinx
- 高级FPGA设计技巧，教你如何综合，如何PR，如何做性能优化，让你一步一步成为FPGA设计高手-Advanced FPGA design skills, teach you how to integrate, how to PR, how to do performance optimization, so you step by step to become a master FPGA Design
LectureNote
- 高级Xilinx FPGA ISE设计教程，详细讲解优化Xilinx设计结构改善时序，减少implementation时间，减少调试时间，片上验证以及调试等FPGA设计深入环节，是深入理解FPGA设计的不可多得的好书。-Advanced Xilinx FPGA ISE design tutorial, explain in detail the structure of the Xilinx design optimization to improve timing, reduce implem
adder128x
- 128位加法器优化设计：64位加法运算+2-1多路选择器。并在关键路径上添加寄存器，降低延迟。 testbench可以测试优化的效果，在ISE中做过综合，能跑到200+MHz-128-bit adder optimization design: 64-bit adder+ 2-1MUX. In the key path, there are regs to improve the performance and reduce the delay time. you use the tes
sine_package
- Sinusoidal generation package for VHDL programme to use with optimization
VHDL-description-
- 2选1多路选择器的VHDL描述四种方法.txt 对于实现同一功能的电路，有不同的描述方法；另一方面，对于既定的电路功能，对应的电路结构不是唯一的，可以对应不同的电路结构，取决于综合器的基本元件库的来源、优化方向和约束的选择。- 2choose 1 multichannel selector VHDL descr iption of four kinds of methods. TXT To realize the same function circuit, there is the
seiqinglao
- Optimization class contains several simple sample programs, MIMO OFDM matlab simulation, Includes the modulation, demodulation, signal to noise ratio calculation.
2672
- Genetic algorithm based reactive power optimization, ML estimation method can be a good signal to noise ratio, Calculation of the Euclidean distance between the two matrices.
modelsim se 10.1a crack
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation