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state_machine
- 三进程有限状态机的设计程序，内附有AD574逻辑控制真值表以及采样状态机的原理图-Third, the process of finite state machine design process, logic control of typhoons and rainstorms are AD574 truth table, as well as sampling state machine schematic
R
- 双向移位寄存器的原理设计程序，对于初学者将会有很大帮助，尤其在设计功能比较复杂的FPGA时，有些问题其实用这个就很简单-The principle of bi-directional shift register the design process, for beginners there will be a great help, especially in the design features of the FPGA more complex, there are some proble
Verilog-book
- 学习Verilog语言必备资料，包括语法总结 编写Verilog HDL 源代码的标准及设计流程-Verilog language learning essential information, including syntax summary of Verilog HDL source code for the preparation of standards and design process
song
- 音乐，梁祝，其中应用VHDL编写的全过程梁祝。-Music, Butterfly Lovers, in which the application of VHDL to prepare the whole process of Butterfly Lovers.
cd
- 通过在进程1中检测时钟上升沿，循环累加，触发进程2，一次输出高电平，使灯发光-1 in the process of testing the clock rising edge, cycle accumulate, triggering the process of 2, a high output, so that LED lamp
modelsimshiyong
- modelsim的详细开发和使用过程 适合初级modelsim学员-ModelSim detailed process of development and use of ModelSim for primary students
internet_FPGA
- 介绍了Xilinx最新的EDK9．1i和ISE9．1i等工具的设计使用流程-Xilinx introduced the latest EDK9.1i and ISE9.1i the use of tools such as the design process
Xilinx_FPGA
- 介绍了FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE-Introduced the entire FPGA design process: Modelsim>> Synplify.Pro>> ISE
FPGA444555443
- 基于FPGA的全数字锁相环设计,内有设计过程和设计思想-FPGA-based all-digital phase-locked loop design, with the design process and design thinking
shumi
- 波形发生器之疏密波的产生，这是一个通过内部选择器来从密波和疏波当中在某一该是选择输出的程序。-Waveform generator of the density wave, and this is an internal selector from thinning dense wave and wave them in a selection of the output process.
seg7_b
- 这是一个用VHDL语言编写的数字电路程序，仅供学习和参考。-This is a language with VHDL digital circuit process, learning and reference purposes only.
Digital_Clock_VHDL
- 使用VHDL开发的简易数字时钟软件，可以作为初学者熟悉定时器应用的实例程序。-Use VHDL to develop a simple digital clock software can be used as timers for beginners familiar with examples of the application process.
watchver
- 一个VHDL编写的时钟的程序，全部源代码打包上传-The clock to prepare a VHDL process, all source code packaged Upload
jiaotongdeng
- 1). 用红、绿、黄三色发光二极管作信号灯。主干道为东西向，有红、绿、黄三个灯；支干道为南北向，也有红、绿、黄三个灯。红灯亮禁止通行；绿灯亮允许通行；黄灯亮则给行驶中的车辆有时间停靠到禁行线之外。 2).由于主干道车辆较多而支干道车辆较少，所以主干道绿灯时间较长。当主干道允许通行亮绿灯时，支干道亮红灯。而支干道允许通行亮绿灯时，主干道亮红灯，两者交替重复。主干道每次放行50秒，支干道每次放行30秒。 在每次由亮绿灯变成亮红灯的转换过程中间，需要亮5秒的黄灯作为过渡，以使行驶中的车辆有时间
machester_VHDL
- manchester码在通信领域中用途广泛 这个VHDL程序包括曼彻斯特码的打包和解包。。很难得哦-manchester code in the communications area of a wide range of uses of this process includes the VHDL code packaged Manchester reconciliation package. . Oh, a rare
key
- 键扫描 处理程序 verilog 使用时钟为50Hz // 低电平为按下,高电平为断开 // 输出状态,1为键入,0为无键-Key scanning process using the clock for Verilog 50Hz// low level for the press, high for the disconnect// output state, one for the type, 0 for no key
ring
- Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, speed grows. The process starts again after last 8 cycle.
jianpanyima
- 利用FPGA编写的键盘译码程序，可以看看！-Keyboard decoding process can take a look at!
pinlvji
- 频率计程序设计与仿真验证，基于VHDL语言-Cymometer process design and simulation verification, based on the VHDL language
zhuangtaiji
- 有限状态机及其设计技术是实用数字系统设计中的重要组成部分,也是实现高效可靠逻辑控制的重要途径,本程序为单进程moore型有限状态机底层设计源代码.-This procedure as a single process moore-type finite state machine underlying the design of the source code.