搜索资源列表
Freq_4
- 伺服电机编码器四倍频源程序，已经在工程中应用。非常有用。-it is important,it has been use in my project.i hope it is useful to everyone
sim_usb_full_interface_tb
- FTDI245B usb project
Test_LED[1]
- 用VHDL实现的一个工程，可以参考来学习FPGA的设计-VHDL achieved with a project, you can reference to learn the design of FPGA
Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_E
- Example VHDL project showing how to use a PWM by CPLD
TrafficLight
- 用vhdl写的交通灯程序，压缩包内有整个工程文件-With the traffic lights to write vhdl procedure, compressed package files have the whole project
Exp1-Led
- 本次实验使用 Xilinx FPGA的开发工具 ISE6.x，新建一个工程，并进行综合、布局布线、 下载配置。 这里建立的工程是使用 Create-SOPCMB上的发光二极管显示一个八位二进制计数器， 发光二极管亮表示该位为 0。 -Experimental use of the Xilinx FPGA development tools ISE6.x, create a new project, and comprehensive, the layout of wiring, d
DE2_70_TV
- 基于NIOS II的电视视频处理工程文件，很完整。-NIOS II on TV video processing project file, it is complete.
pinlvji
- 等精度频率计设计，很好的源代码，附上工程文件，在quartus5.0以上版本即可运行。-Design accuracy, such as frequency meter, a good source code, attached to the project document, in the above quartus5.0 to run.
1508
- 是CPLD内的程序 控制6个电机，同时还用液晶显示的图的工程中采用了cpld-CPLD program is within the six motors, but also plans to use liquid crystal display used in the project cpld
FSK_FPGA
- FSK模拟信号源，利用ISE7.1或以上环境打开。-FSK signal simulator.The project can be open in ISE7.1 or upgrade version.
1
- 毕业设计手册模版--数字滤波器的FPGA实现南才北往 毕业设计手册模版--数字滤波器的FPGA实现南才北往 -Graduation project handbook template- the FPGA realization of digital filters to the north to the south graduated from Design Manual template- the FPGA realization of digital filters to the nort
etester_zcx1002
- 这是一个等精度频率计的VHDL源程序，里面有QuartusII的完整工程文件。-This is a precision frequency meter, such as the VHDL source code, which has a complete project file QuartusII.
3
- 基于FPGA的任意信号发生器，毕业设计完整稿，适合做毕设的同学参考-FPGA-based arbitrary signal generator, a complete draft graduation project, suitable for students to complete reference
dds_easy
- 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be dir
IIRtest
- quartusII9.0开发环境下巴特沃斯IIR滤波器的实现完整的工程文件，同时里面有文档详细说明如何用modelsim对altera芯片进行仿真-development environment quartusII9.0 Butterworth IIR filter to achieve a complete project file, but there are documents in detail how to use modelsim to altera-chip simulation
URAT_VHDL
- FPGA采用模块工程文件QUARTUS II工程、ADC0809、电机控制PWM、LCD12864显示控制、UART_VHDL-FPGA module QUARTUS II project engineering documents, ADC0809, motor control PWM, LCD12864 display control, UART_VHDL
S5_UART
- verilog编写的UART程序，是红色飓风EP1C6板子上面的程序-this is a UART project with verilog language,it is the programmer by the redlogic s EP1C6 board
uart_Transmitter
- 自己写的一个uart驱动代码，是一个工程文件，适合初学者，里面的状态机的写法十分值得学习-To write a uart driver code, is a project file, suitable for beginners, which the wording of the state machine is worth learning
serial_xiangguan
- 用verilog编写的一个相关检测的工程，注释比较详细，里面的算法理解起来可能会有一定的难度-Verilog prepared with detection of a related project, more detailed comments, which the algorithm may be understood to a certain degree of difficulty
counter
- Counter for VHDL Project