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SPI3_8bit
- 一整套通用的用Verilog代码实现的SPI3接口（8bit接口）协议代码，包含ISE工程文件，本代码在Xilinx公司的FPGA上实现，并且有Modelsim仿真的源文件-SPI3 verilog code（including ISE project and modelsim code)
Quartus_II_7.0.rar
- Quartus II 7.0工程修复大法。修复不能打开的工程。有人在7.2的软件下用本方法也成功修复。 他是修复这个错误： Error: Can t open project -- you do not have permission to write to all the files or create new files in the project s database directory,Quartus II 7.0 Dafa repair works. Restoration pr
T6_SRAM.rar
- SRM读写检验的程序，是红色飓风EP1C6板子上面的例程,SRM s read and write project.it s the example project of redlogic s EP1C6 board.
VHDL语言实现的arm内核
- 5个ram核，arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核，verilog写的，有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心，结构良好，简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目，国防科技大学牛人ShengYu Shen写的，原来放在opencores上，
susliks-project
- 基于逻辑门的打地鼠游戏，其中设置了三关，每关出现八个地鼠-playing susliks with logic gate
DUC.rar
- 基于XILINX ISE下的数字上变频设计，其中用到了XILINX的乘法IP。已经通过工程实用，好用。,XILINX ISE based on frequency of figure design, use one of the XILINX multiplication IP. Has passed the project practical, easy to use.
SRAM
- 使用方法： SRAM编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: SRAM programming, copied to the hard drive, open the project file with ISE can
canbus
- CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
fpga-dm9000a
- 一个项目工程，硬件包含XINLINX FPGA，配置FLASH，串口，SDRAM,与以太网芯片DM9000A，实现数据采集，以太网传输，电路验证完全正确，请放心使用，SPARTAN 3E 的BGA引脚320个，不容易布板，可以参考使用的。要FPGA实现网络通信也可以参考电路，B因为产品升级了所以公开原来的电路的。 -A project engineering, hardware contains XINLINX FPGA, configuration FLASH, serial port, SD
eth_send
- 清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。-Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.
GPS.RAR
- 本工程包含了一个GPS接收机的基带处理模块，包括信号捕获和跟踪、电文解调等-The project includes a GPS receiver baseband processing modules, including signal acquisition and tracking, message demodulation
fredevide
- 用FPGA仿真实现数控分频器，完整的工程文件-FPGA simulation of nc prescalar, including complete project files
FSMLibrary
- 有限状态机源码，最近在做一个项目需要用到状态机，自己研究了一下，将原来的状态机封装了，做了一些修改，实现了一个比较好用的状态机。里面包括测试工程，用例-Finite state machine source code, most recently doing a project needs to use state machines, their study a little, the original state machine package, and made some modificat
YCbCr_RGB_10bit
- YCbCr 转 RGB模块，以应用于项目中。 该模块可将10bitYCbCr分量视频转换为12bitRGB视频，需消耗乘法器。-YCbCr turn RGB module, to apply to the project. The module can be 10bitYCbCr component video converted to 12bitRGB video, need to consume multiplier.
AssignmentP3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx
Core8051
- VERILOG编写的Core8051实验例程，包括整个工程，周立功公司提供-VERILOG Core8051 written test routines, including the entire project, provided ZLG
Quartusii
- quartus2的简明教程，讲述了建立以个工程的基本步骤，很快上手-The Concise Guide quartus2, described a project to establish the basic steps to start soon
ptpress
- Altera FPGACPLD设计(高级篇)配套光盘,提供了书中所有示例的完整工程文件、设计源文件和说明文件。 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Altera FPGACPLD Design (Advanced papers) supporting CD-ROM, the book provides a complete project files fo
spi
- SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
user_logic_0
- 基于microblaze EDK 工程，实现六种RFID 协议的ip core。-Based on microblaze EDK project, to achieve the six RFID protocol ip core.