搜索资源列表
adaptive_lms_equalizer_latest.tar
- In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
audio_project
- Enhanced Audio Project by Dixie Xue & Wei Zhang -Enhanced Audio Project by Dixie Xue & Wei Zhang
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by defau
8255A2.9
- 采用Verilog语言实现了8255A的功能，并下载到了FPGA上进行了验证-this project achieved the goal of realizing the function of 8255A which is widely used in many digital designs.
Project
- 定制一个双端口RAM，DualPortRAM-RAM，DualPortRAM
Project
- 熟悉Altera IP的产生和实现方法定制一个8B10B编码器- 8B10B codeer
Upload
- Hello Everyone, this site provides useful document to students like me those who are starts doing project in Programming field.
efcount
- 完整的等精度频率相位计，包含了项目文件、VHDL源代码、RTL电路图-Such as the complete phase of the frequency accuracy, including the project document, VHDL source code, RTL circuit
count10
- 基于Quartus II的十进制加法计数器的项目设计，包含了项目文件和VHDL源代码-Quartus II based on the decimal adder counter the project design, including project documents and VHDL source code
fdiv
- 基于Quartus II的数控分频器的项目设计，实现对时钟信号的任意进制分频，包含了项目文件和VHDL源代码-NC-based prescaler Quartus II project design, implementation of the clock signal of arbitrary frequency band, including the project files and VHDL source code
f_cout
- 基于Quartus II的8位十六进制频率计的项目设计，包含了项目文件和VHDL源代码-Quartus II-based 8-bit hexadecimal frequency of project design, including project documents and VHDL source code
23-10111
- a simple serial to parallel converter using XILLINX and VHDL (the number of the project represents the binary code used by the converter e.g 23- 10111)
cfft_latest.tar
- VHDL 1024 FFT PROJECT
document2007620132345
- Project Name : SOPC-based Voiceprint Identification System
CPU
- 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended
dds
- DDS数字频率合成器，使用很方便，整个工程下载，vhdl语言-DDS digital frequency synthesizer, using the very convenient to download the whole project, vhdl language
USB2_V
- USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.-USB2_V example FPGA project is a data transmitted to the PC through the USB2.0 sample machine.
USB20
- USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.-USB2_V example FPGA project is a data transmitted to the PC through the USB2.0 sample machine.
HardCamera
- The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable