搜索资源列表
trunk-hdlc.rar
- 高级链路层协议的实现,vhdl,fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
pn127
- 这是个128位的串行伪随机码发生器,还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded
fcsr
- 伪随机序列产生器-代进位反馈移位寄存器,verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
ffcsr
- 伪随机序列产生器-filtered 代进位反馈移位寄存器,verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
Application_of_pseudo_random_sequence_verilog_desi
- 伪随机序列应用verilog设计.rar-Application of pseudo-random sequence verilog design.rar
VHDL
- 8*8乘法器设计 伪随机序列发生器 PS2键盘设计 均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
random
- Verilog使用$random()函數簡單範例-Verilog using the $ random () function of a simple example
pwm
- :随机脉宽调制是解决交流调速系统 中声学噪声的直接有效方法。随机零矢 量分 布是一种很好 的随 机方法,但其不对称的开关函数使其不适用于传统的电流采样方法。通过仿真表明 PWM周期中点采样的方 法无法得到准确的平均值,在分析不对称模式引起的纹波电流对电流平均值影响的基础上,提出了一种适合 于 RZV分布 的电流采样方法 。仿真结果证实该方法简单可行 。 -: Random pulse width modulation speed control system to solve
PWM_DA
- 随着电子技术的发展,出现了多种PWM技术,其中包括:相电压控制PWM、脉宽PWM法、随机PWM、SPWM法、线电压控制PWM等,而在镍氢电池智能充电器中采用的脉宽PWM法,它是把每一脉冲宽度均相等的脉冲列作为PWM波形,通过改变脉冲列的周期可以调频,改变脉冲的宽度或占空比可以调压,采用适当控制方法即可使电压与频率协调变化。可以通过调整PWM的周期、PWM的占空比而达到控制充电电流的目的。-With the development of electronic technology, a varie
Pseudo_Random_Num_Generator
- The file included is the source code for Pseudo Random Generator
random
- random number generator... tt8-random number generator... tt800
pseudo-random-sequence-generator-
- 利用FPGA编程--- -实现“伪随机序列发生器设计”-FPGA programming------- pseudo-random sequence generator design
random
- 随机数产生以及发牌程序 包括test的tb程序-Random number generator and licensing procedures, including test
Pseudo-random
- 伪随机序列FPGA应用设计代码 Pseudo-random sequence-Pseudo-random sequence of application design
random
- 8位伪随机序列发生器。在通信加扰,序列检测中有很强的工程应用-8 pseudo-random sequence generator. In communications scrambling sequence detection has a strong engineering applications
Pseudo-Random
- Pseudo Random Sequence Generator Code and Tutor
random
- 伪随机序列应用设计,应用与产生伪随机序列,FPGA实现-Pseudo-random sequence application design, application and generate a pseudo-random sequence, FPGA realization
Random-number-generator-verilog
- Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.
pseudo-random-number-VHDL
- 伪随机序列发生器的vhdl软件,有m序列和gold序列的算法-pseudo random number generator
Random-sequence-of-test
- 随机序列的测试源码,使用verilog编写,感觉很有用,希望大家喜欢-Random sequence of test source, the use verilog to write, feel useful, I hope you like