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div_n
- verilog占空比50奇偶任意 奇偶任意分频器！包括测试代码-verilog random duty cycle of 50 odd parity arbitrary divider! Including test code
weisuijitu
- 伪随机图生成程序，包括时钟频率的合成、分别以比特和字节方式生成伪随机图模块。-Pseudo-random graph generation procedures, including the clock frequency synthesis means bits and bytes, respectively pseudo-random graph generation module.
yinyue
- 音频播放器 音频播放器可播放三首不同的歌曲，可实现，上一首，下一首，随机播放等功能，需和硬件相连接-Audio player audio player can play three different songs, can be realized, on the one, next, random play functions, and hardware required to connect
noise
- 随机噪声产生代码。所输出的随机噪声可以用于模拟信道中的加性噪声。-Random noise generated code. The output of the random noise can be used to simulate the channel additive noise.
RAM
- The files attached include the excuted output files for the access of Random Access Memeory
ROM
- 本代码实现的是生成随机数的verilog 代码。可在ModelSim中仿真-The code is the verilog code to generate random numbers. In the simulation in the ModelSim
LCD1602
- 写的一个用lcd1602的随机数发生器，用的语言为Verilog，工具是Quartus II软件。-Write a random number generator with lcd1602, the language used for the Verilog, Quartus II software tool.
RNG
- True random generation
Quartus
- Quartus程序是滤波器+功率检测+相关计算+TDD时隙切换，从滤波输出的过采样信号中随机指定输出其中的一路信号输出用来做功率检测和相关计算，相关计算完全采用串行计算比较的方式得到最大值，然后根据这个最大值的位置推算出上、下行时隙的切换点位置。-Filter+ Quartus program is related to computing power detection++ TDD time slot switch, from the filtered output signal over a
ram
- vhdl program for random access memory and sequence detector
eeprom1
- nios II下EEPROM程序设计，EEPROM采用24LC04，包括读写程序，读程序包括随机读，当前读，连续读。写包括随机写，页写。-nios II under the EEPROM programming, EEPROM with 24LC04, including literacy programs, reading programs, including random read, the current reading, continuous reading. Write includ
PN4
- 语言：VHDL 功能：该PN4序列的特点为将一个4位序列的前两位取异或，再让序列左移一位，用异或的结果作为序列的最后一位。序列周期是15，即15位伪随机序列。其中包括序列的产生模块和检测模块。对于误码检测，首先捕获相位。然后，规定测试的码的总个数，统计这些码中有多少个不能满足PN序列特点的，用计数器统计个数。如果发现误码过多，可能是相位失调，重新捕获相位，再进行误码检测。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function:
interlace
- 根据MATLAB中的伪随机交织器产生的交织图案初始化到ROM中，从ROM中读取交织图案对输入数据进行交织。同时也可根据解交织图案进行解交织，同样的算法。-In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can a
sram_8_8
- 该程序实现8*8位的静态随机存储器功能，已通过仿真验证，程序运行无误。-The program realization of 8* 8-bit static random access memory function, has been verified by simulation, the program runs correctly.
pseudo-randomcodegenerator
- VERILOG语言编写的伪随机码产生器，可以ISE中编绎调试-VERILOG language of pseudo-random code generator, you can unravel ISE in debugging code
prbs
- 伪随机二进制序列发生器的Verilog源码，带测试文件，并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board
dianzhen(ok)
- 驱动8*8点阵块显示汉字，可以自己根据要显示的内容随意更改，已通过验证。-Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.
shift_register
- It is noise generator.it is a linear feedback 16 shift-registe where the bits 15,14,12,3 are fed back via xor gates.make random signal close to real noise
randon_numder_generator
- random number generator it generate random number continousely on clk pulse
Writing-Testbenches-using-System-Verilog.tar
- Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from