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seg
- 7段数码管显示的VHDL语言，适合初学者用，相当不错的
SSC
- Implement the 7 segment diplay on spartan 3
freq_meter
- Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.
SEG
- 7段译码器 吉林大学短学期CPLD实习程序 通过四位拨码开关进行编码，让硬件电路将编码转换成对应的七段码，并将七段码送至数码管进行显示，其中该电路能够输出0到F的16个字符-7 decoder CPLD Jilin University internship program through short-term four DIP switch coded, so that hardware will be encoded into the corresponding seven-segmen
leds_7segs
- Sample code for VDHL, 7 seg.
7-seg-display
- 数码管动态显示程序，使用VHDL编写的程序，可移植性好-Digital dynamic display program, the use of VHDL procedures, portability
SEG7lED
- 基于verilog的7段数码管显示控制，实现数字显示。-7 seg led displaying control based on verilog
SEG-1
- this code show to use Altium to coding Single 7 Segment on FPGA-CPLD -this code show how to use Altium to coding Single 7 Segment on FPGA-CPLD
SegSimplified
- 本工程使用verilog HDL和vivado2014集成开发环境实现利用xilinx Basys3开发板上4位数码管显示从0到9999的计数器功能。-This project uses verilog HDL to realise counting 0 to 9999 on the 7-seg LED loaded on Xilinx Basys3 board.
seg
- 7段数码管驱动，基于MAX II EPM40-7 u6BB5 u6570 u7801 u7BA1 u9A71 u52A8