本代码功能为实现接收PC发送的串口数据功能 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions to achieve the receivi

VHDL实现串口功能，可以直接拷贝使用。祝大家用得开心-Serial functional VHDL, you can use directly copy. I wish you all much happier with

深入浅出玩转FPGA一书中实验中的串口读写实验-Fun FPGA simple terms, a book to read and write from serial com.

this a serial port (COM) transmitter module and it is fully synthesizble on fpga it has load, clk, rest and data inputs and serial a,d busy outpus -this is a serial port (COM) transmitter module and it is fully synthesizble on fpga it has load, c